| 2007 |
|---|
| 5 | EE | Rouwaida Kanj,
Rajiv V. Joshi,
Jayakumaran Sivagnaname,
Jente B. Kuang,
Dhruva Acharyya,
Tuyet Nguyen,
Chandler McDowell,
Sani R. Nassif:
Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs.
ISQED 2007: 33-40 |
| 2006 |
|---|
| 4 | EE | Jim Plusquellic,
Dhruva Acharyya,
Abhishek Singh,
Mohammad Tehranipoor,
Chintan Patel:
Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method.
IEEE Design & Test of Computers 23(4): 278-293 (2006) |
| 2005 |
|---|
| 3 | EE | Dhruva Acharyya,
Jim Plusquellic:
Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements.
VTS 2005: 433-438 |
| 2003 |
|---|
| 2 | EE | Dhruva Acharyya,
Jim Plusquellic:
Impedance Profile of a Commercial Power Grid and Test System.
ITC 2003: 709-718 |
| 1 | EE | Chintan Patel,
Ernesto Staroswiecki,
Smita Pawar,
Dhruva Acharyya,
Jim Plusquellic:
Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids.
J. Electronic Testing 19(6): 611-623 (2003) |
