2008 |
23 | | Fabien Soulier,
Lionel Gouyet,
Guy Cathébras,
Serge Bernard,
David Guiraud,
Yves Bertrand:
Considerations on Improving the Design of CUFF Electrode for ENG Recording - Geometrical Approach, Dedicated IC, Sensitivity, Noise Rejection.
BIODEVICES (2) 2008: 180-185 |
22 | EE | Fabien Soulier,
Jean-Baptiste Lerat,
Lionel Gouyet,
Serge Bernard,
Guy Cathébras:
A Neural Stimulator Output Stage for Dodecapolar Electrodes.
ISVLSI 2008: 487-490 |
2007 |
21 | EE | Philippe Cauvet,
Serge Bernard,
Michel Renovell:
System-in-Package, a Combination of Challenges and Solutions.
European Test Symposium 2007: 193-199 |
20 | EE | Vincent Kerzerho,
Philippe Cauvet,
Serge Bernard,
Florence Azaïs,
Mariane Comte,
Michel Renovell:
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC.
European Test Symposium 2007: 211-216 |
2006 |
19 | EE | Vincent Kerzerho,
Philippe Cauvet,
Serge Bernard,
Florence Azaïs,
Mariane Comte,
Michel Renovell:
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC.
European Test Symposium 2006: 159-164 |
18 | EE | V. Fresnaud,
Lilian Bossuet,
Dominique Dallet,
Serge Bernard,
J. M. Janik,
B. Agnus,
Philippe Cauvet,
Ph. Gandy:
A Low Cost Alternative Method for Harmonics Estimation in a BIST Context.
European Test Symposium 2006: 193-198 |
17 | EE | Vincent Kerzerho,
Philippe Cauvet,
Serge Bernard,
Florence Azaïs,
Mariane Comte,
Michel Renovell:
A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs.
IEEE Design & Test of Computers 23(3): 234-243 (2006) |
16 | EE | Vincent Kerzerho,
Serge Bernard,
Philippe Cauvet,
J. M. Janik:
A First Step for an INL Spectral-Based BIST: The Memory Optimization.
J. Electronic Testing 22(4-6): 351-357 (2006) |
2005 |
15 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Mariane Comte,
Michel Renovell:
Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications.
J. Electronic Testing 21(3): 291-298 (2005) |
2004 |
14 | EE | Serge Bernard,
Mariane Comte,
Florence Azaïs,
Yves Bertrand,
Michel Renovell:
Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors.
J. Electronic Testing 20(3): 257-267 (2004) |
13 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Mariane Comte,
Michel Renovell:
Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure.
J. Electronic Testing 20(4): 375-387 (2004) |
2003 |
12 | EE | Serge Bernard,
Mariane Comte,
Florence Azaïs,
Yves Bertrand,
Michel Renovell:
A New Methodology For ADC Test Flow Optimization.
ITC 2003: 201-209 |
11 | EE | Serge Bernard,
Florence Azaïs,
Yves Bertrand,
Michel Renovell:
On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST.
J. Electronic Testing 19(4): 469-479 (2003) |
10 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Mariane Comte,
Michel Renovell:
A-to-D converters static error detection from dynamic parameter measurement.
Microelectronics Journal 34(10): 945-953 (2003) |
2002 |
9 | EE | Yves Bertrand,
Marie-Lise Flottes,
Florence Azaïs,
Serge Bernard,
Laurent Latorre,
Regis Lorival:
European Network for Test Education.
DELTA 2002: 230-234 |
2001 |
8 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Michel Renovell:
Implementation of a linear histogram BIST for ADCs.
DATE 2001: 590-595 |
7 | EE | Serge Bernard,
Florence Azaïs,
Yves Bertrand,
Michel Renovell:
Analog BIST Generator for ADC Testing.
DFT 2001: 338-346 |
6 | | Michel Renovell,
Jean Marc Gallière,
Florence Azaïs,
Serge Bernard,
Yves Bertrand:
Boolean and current detection of MOS transistor with gate oxide short.
ITC 2001: 1039-1048 |
5 | | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Michel Renovell:
On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST.
VLSI-SOC 2001: 425-436 |
4 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Xavier Michel,
Michel Renovell:
A Low-Cost Adaptive Ramp Generator for Analog BIST Applications.
VTS 2001: 266-271 |
3 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Michel Renovell:
A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs.
J. Electronic Testing 17(2): 139-147 (2001) |
2 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Michel Renovell:
Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST.
J. Electronic Testing 17(3-4): 255-266 (2001) |
2000 |
1 | EE | Michel Renovell,
Florence Azaïs,
Serge Bernard,
Yves Bertrand:
Hardware Resource Minimization for Histogram-Based ADC BIST.
VTS 2000: 247-254 |