| 2006 |
|---|
| 75 | EE | Yoshiyuki Nakamura,
Jacob Savir,
Hideo Fujiwara:
BIST Pretest of ICs: Risks and Benefits.
VTS 2006: 142-149 |
| 74 | EE | Yoshiyuki Nakamura,
Jacob Savir,
Hideo Fujiwara:
Effect of BIST Pretest on IC Defect Level.
IEICE Transactions 89-D(10): 2626-2636 (2006) |
| 2005 |
|---|
| 73 | EE | Yoshiyuki Nakamura,
Jacob Savir,
Hideo Fujiwara:
Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST.
IEICE Transactions 88-D(6): 1210-1216 (2005) |
| 72 | EE | Zhiqiang You,
Ken-ichi Yamaguchi,
Michiko Inoue,
Jacob Savir,
Hideo Fujiwara:
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths.
IEICE Transactions 88-D(8): 1940-1947 (2005) |
| 2004 |
|---|
| 71 | EE | Zhiqiang You,
Ken-ichi Yamaguchi,
Michiko Inoue,
Jacob Savir,
Hideo Fujiwara:
Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths.
Asian Test Symposium 2004: 32-39 |
| 70 | EE | Amit M. Sheth,
Jacob Savir:
Scan Latch Design for Test Applications.
J. Electronic Testing 20(2): 213-216 (2004) |
| 2003 |
|---|
| 69 | EE | Zhen Guo,
Jacob Savir:
Analog Circuit Test using Transfer Function Coe .cient Estimates.
ITC 2003: 1155-1163 |
| 2002 |
|---|
| 68 | EE | Jacob Savir,
Zhen Guo:
Test Limitations of Parametric Faults in Analog Circuits.
Asian Test Symposium 2002: 39-44 |
| 67 | EE | Zhen Guo,
Jacob Savir:
Observer-Based Test of Analog Linear Time-Invariant Circuits.
DELTA 2002: 13-17 |
| 66 | EE | Jacob Savir,
Zhen Guo:
On the Detectability of Parametric Faults in Analog Circuits.
ICCD 2002: 273-276 |
| 2001 |
|---|
| 65 | EE | Zhen Guo,
Xi Min Zhang,
Jacob Savir,
Yun-Qing Shi:
On Test and Characterization of Analog Linear Time-Invariant Circuits Using Neural Networks.
Asian Test Symposium 2001: 338-343 |
| 2000 |
|---|
| 64 | EE | Jacob Savir:
On testing safety-sensitive digital systems.
Asian Test Symposium 2000: 478-483 |
| 63 | | Jacob Savir:
On-line and off-line test of airborne digital systems: a reliability study.
ITC 2000: 35-44 |
| 62 | | Qiang Peng,
Miron Abramovici,
Jacob Savir:
MUST: multiple-stem analysis for identifying sequentially untestable faults.
ITC 2000: 839-846 |
| 61 | EE | Jacob Savir:
Distributed BIST Architecture to Combat Delay Faults.
J. Electronic Testing 16(4): 369-380 (2000) |
| 1999 |
|---|
| 60 | EE | Jacob Savir:
Memory Chip BIST Architecture.
Great Lakes Symposium on VLSI 1999: 384- |
| 59 | EE | Jacob Savir:
Design for Testability to Combat Delay Faults.
ICCD 1999: 407-411 |
| 58 | EE | Jacob Savir:
Distributed Generation of Weighted Random Patterns.
IEEE Trans. Computers 48(12): 1364-1368 (1999) |
| 57 | EE | Jacob Savir:
Random Pattern Testability of Control and Address Circuitry of an Embedded Memory with Feed-Forward Data-Path Connections.
J. Electronic Testing 15(3): 279-296 (1999) |
| 1998 |
|---|
| 56 | EE | Jacob Savir:
BIST Diagnostics, Part 1: Simulation Models.
Asian Test Symposium 1998: 8-14 |
| 55 | EE | Jacob Savir:
Distributed Generation of Weighted Random Patterns.
VTS 1998: 225-233 |
| 54 | | Jacob Savir:
Random Pattern Testability of Memory Control Logic.
IEEE Trans. Computers 47(3): 305-312 (1998) |
| 53 | | Jacob Savir:
Salvaging Test Windows in BIST Diagnostics.
IEEE Trans. Computers 47(4): 486-491 (1998) |
| 52 | EE | Jacob Savir:
Redundancy revisited.
IEEE Trans. VLSI Syst. 6(4): 620-624 (1998) |
| 51 | EE | Jacob Savir:
Random pattern testability of memory address logic.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1310-1318 (1998) |
| 50 | EE | Jacob Savir:
On-Chip Weighted Random Patterns.
J. Electronic Testing 13(1): 41-50 (1998) |
| 1997 |
|---|
| 49 | EE | Jacob Savir:
On The Tradeoff Between Number of Clocks and Number of Latches in Shift Registers.
Asian Test Symposium 1997: 296-299 |
| 48 | EE | Jacob Savir:
On Chip Weighted Random Patterns.
Asian Test Symposium 1997: 343-352 |
| 47 | | Jacob Savir:
BIST-Based Fault Diagnosis in the Presence of Embedded Memories.
ICCD 1997: 37-47 |
| 46 | | Jacob Savir:
Scan Latch Design for Delay Test.
ITC 1997: 446-453 |
| 45 | EE | Jacob Savir:
Random pattern testability of memory control logic.
VTS 1997: 399-409 |
| 44 | EE | Jacob Savir:
Salvaging test windows in BIST diagnostic.
VTS 1997: 416-425 |
| 43 | EE | Jacob Savir:
Delay Test Generation: A Hardware Perspective.
J. Electronic Testing 10(3): 245-254 (1997) |
| 42 | EE | Jacob Savir:
Module Level Weighted Random Patterns.
J. Electronic Testing 10(3): 283-287 (1997) |
| 41 | EE | Jacob Savir:
Reduced Latch Count Shift Registers.
J. Electronic Testing 11(2): 183-185 (1997) |
| 1996 |
|---|
| 40 | EE | Sandeep K. Gupta,
Slawomir Pilarski,
Sudhakar M. Reddy,
Jacob Savir,
Prab Varma:
Delay Fault Testing: How Robust are Our Models?
VTS 1996: 502-503 |
| 39 | | Jacob Savir:
Reducing the MISR Size.
IEEE Trans. Computers 45(8): 930-938 (1996) |
| 1995 |
|---|
| 38 | EE | Jacob Savir:
Generator choices for delay test.
Asian Test Symposium 1995: 214-221 |
| 37 | EE | Jacob Savir:
Module level weighted random patterns.
Asian Test Symposium 1995: 274-278 |
| 36 | EE | Jacob Savir:
On shrinking wide compressors.
VTS 1995: 108-117 |
| 35 | EE | Jacob Savir:
Shrinking wide compressors [BIST].
IEEE Trans. on CAD of Integrated Circuits and Systems 14(11): 1379-1387 (1995) |
| 1994 |
|---|
| 34 | EE | Jacob Savir,
Srinivas Patil:
On broad-side delay test.
IEEE Trans. VLSI Syst. 2(3): 368-372 (1994) |
| 33 | EE | Jacob Savir,
Srinivas Patil:
Broad-side delay test.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(8): 1057-1064 (1994) |
| 1993 |
|---|
| 32 | EE | Jacob Savir,
Srinivas Patil:
Scan-based transition test.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1232-1241 (1993) |
| 1992 |
|---|
| 31 | | Jacob Savir:
Skewed-Load Transition Test: Part 1, Calculus.
ITC 1992: 705-713 |
| 30 | | Srinivas Patil,
Jacob Savir:
Skewed-Load Transition Test: Part 2, Coverage.
ITC 1992: 714-722 |
| 29 | | A. Boneh,
Jacob Savir:
Statistical Resistance to Detection.
IEEE Trans. Computers 41(1): 123-126 (1992) |
| 28 | | Jacob Savir,
William H. McAnney:
A Multiple Seed Linear Feedback Shift Register.
IEEE Trans. Computers 41(2): 250-252 (1992) |
| 27 | EE | Jacob Savir,
Robert F. Berry:
AC strength of a pattern generator.
J. Electronic Testing 3(2): 119-125 (1992) |
| 1991 |
|---|
| 26 | | Jacob Savir,
Robert F. Berry:
At-Speed Test is not Necessarily an AC Test.
ITC 1991: 722-728 |
| 25 | | Jacob Savir,
William H. McAnney,
Salvatore R. Vecchio:
Testing for Coupled Cells in Random-Access Memories.
IEEE Trans. Computers 40(10): 1177-1180 (1991) |
| 24 | EE | Jacob Savir,
Paul H. Bardell:
Partitioning of polynomial tasks: test generation, an example.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(11): 1465-1468 (1991) |
| 1989 |
|---|
| 23 | | Jacob Savir,
William H. McAnney,
Salvatore R. Vecchio:
Testing for Coupled Cells in Random-Access Memories.
ITC 1989: 439-451 |
| 1988 |
|---|
| 22 | EE | Jacob Savir:
Why Partial Design Verification Works Better Than It Should.
DAC 1988: 704-707 |
| 21 | | Jacob Savir,
William H. McAnney:
Identification of Failing Tests with Cycling Registers.
ITC 1988: 322-328 |
| 20 | | Jacob Savir,
William H. McAnney:
Random Pattern Testability of Delay Faults.
IEEE Trans. Computers 37(3): 291-300 (1988) |
| 19 | | William H. McAnney,
Jacob Savir:
Built-In Checking of the Correct Self-Test Signature.
IEEE Trans. Computers 37(9): 1142-1145 (1988) |
| 1987 |
|---|
| 18 | | Jacob Savir,
William H. McAnney,
Salvatore R. Vecchio:
Fault Propagation Through Embedded Multiport Memories.
IEEE Trans. Computers 36(5): 592-602 (1987) |
| 1986 |
|---|
| 17 | | Jacob Savir,
William H. McAnney:
Random Pattern Testability of Delay Faults.
ITC 1986: 263-273 |
| 16 | | William H. McAnney,
Jacob Savir:
Built-In Checking of the Correct Self-Test Signature.
ITC 1986: 54-59 |
| 15 | | Jacob Savir:
The Bidirectional Double Latch (BDDL).
IEEE Trans. Computers 35(1): 65-66 (1986) |
| 1985 |
|---|
| 14 | | Jacob Savir,
William H. McAnney,
Salvatore R. Vecchio:
Random Pattern Testing for Data-Line Faults in an Embedded Multiport Memory.
ITC 1985: 100-105 |
| 13 | | Jacob Savir,
William H. McAnney,
Salvatore R. Vecchio:
Random Pattern Testing for Address-Line Faults in an Embedded Multiport Memory.
ITC 1985: 106-114 |
| 12 | | Thomas H. Spencer,
Jacob Savir:
Layout Influences Testability.
IEEE Trans. Computers 34(3): 287-290 (1985) |
| 1984 |
|---|
| 11 | | Jacob Savir,
Gary S. Ditlow,
Paul H. Bardell:
Random Pattern Testability.
IEEE Trans. Computers 33(1): 79-90 (1984) |
| 10 | | Jacob Savir,
Paul H. Bardell:
On Random Pattern Test Length.
IEEE Trans. Computers 33(6): 467-474 (1984) |
| 1983 |
|---|
| 9 | | Jacob Savir,
Paul H. Bardell:
On Random Pattern Test Length.
ITC 1983: 95-107 |
| 8 | | Jacob Savir:
A New Empirical Test for the Quality of Random Integer Generators.
IEEE Trans. Computers 32(10): 960-961 (1983) |
| 7 | | Jacob Savir:
Good Controllability and Observability Do Not Guarantee Good Testability.
IEEE Trans. Computers 32(12): 1198-1200 (1983) |
| 1981 |
|---|
| 6 | | Zeev Barzilai,
Jacob Savir,
George Markowsky,
Merlin G. Smith:
VLSI Self-Testing Based on Syndrome Techniques.
ITC 1981: 102-109 |
| 5 | | Zeev Barzilai,
Jacob Savir,
George Markowsky,
Merlin G. Smith:
The Weighted Syndrome Sums Approach to VLSI Testing.
IEEE Trans. Computers 30(12): 996-1000 (1981) |
| 4 | | Jacob Savir:
Syndrome-Testing of ``Syndrome-Untestable'' Combinational Circuits.
IEEE Trans. Computers 30(8): 606-608 (1981) |
| 1980 |
|---|
| 3 | | Jacob Savir:
Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection.
IEEE Trans. Computers 29(5): 410-416 (1980) |
| 2 | | Jacob Savir:
Syndrome-Testable Design of Combinational Circuits.
IEEE Trans. Computers 29(6): 442-451 (1980) |
| 1 | | Jacob Savir:
Detection of Single Intermittent Faults in Sequential Circuits.
IEEE Trans. Computers 29(7): 673-678 (1980) |
