| 2006 |
|---|
| 10 | EE | Aman Kokrady,
Theo J. Powell,
S. Ramakrishnan:
Reducing Design Verification Cycle Time through Testbench Redundancy.
VLSI Design 2006: 243-248 |
| 2003 |
|---|
| 9 | EE | Theo J. Powell,
Wu-Tung Cheng,
Joseph Rayhawk,
Omer Samman,
Paul Policke,
Sherry Lai:
BIST for Deep Submicron ASIC Memories with High Performance Application.
ITC 2003: 386-392 |
| 2000 |
|---|
| 8 | EE | Theo J. Powell,
James R. Pair,
Melissa St. John,
Doug Counce:
Delta Iddq for Testing Reliability.
VTS 2000: 439-443 |
| 1997 |
|---|
| 7 | | Theo J. Powell,
Dan Cline,
Francis Hii:
A 256Meg SDRAM BIST for Disturb Test Application.
ITC 1997: 200-208 |
| 1996 |
|---|
| 6 | | Theo J. Powell,
James R. Pair,
Bernard G. Carbajal III:
Correlating Defects to Functional and IDDQ Tests.
ITC 1996: 501-510 |
| 5 | EE | Theo J. Powell:
Consistently dominant fault model for tristate buffer nets.
VTS 1996: 400-404 |
| 1995 |
|---|
| 4 | | Graham Hetherington,
Greg Sutton,
Kenneth M. Butler,
Theo J. Powell:
Test Generation and Design for Test for a Large Multiprocessing DSP.
ITC 1995: 149-156 |
| 1988 |
|---|
| 3 | | Theo J. Powell,
Fred Hwang,
Bill Johnson:
Testability Features in the TMS370 Family of Microcomputers.
ITC 1988: 153-160 |
| 1982 |
|---|
| 2 | | Satish M. Thatte,
D. S. Ho,
H.-T. Yuan,
Thirumalai Sridhar,
Theo J. Powell:
An Architecture for Testable VLSI Processors.
ITC 1982: 484-493 |
| 1 | | Thirumalai Sridhar,
D. S. Ho,
Theo J. Powell,
Satish M. Thatte:
Analysis and Simulation of Parallel Signature Analyzers.
ITC 1982: 656-661 |
