2009 |
11 | EE | Richard Buchmann,
Mickael Cartron,
Yannick Bonhomme:
Transaction-based modeling for large scale simulations of heterogeneous systems.
SimuTools 2009: 33 |
2006 |
10 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
A Gated Clock Scheme for Low Power Testing of Logic Cores.
J. Electronic Testing 22(1): 89-99 (2006) |
2005 |
9 | EE | Patrick Girard,
Yannick Bonhomme:
Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing.
J. Low Power Electronics 1(1): 85-95 (2005) |
2004 |
8 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Design of Routing-Constrained Low Power Scan Chains.
DATE 2004: 62-67 |
7 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel:
Design of Routing-Constrained Low Power Scan Chains.
DELTA 2004: 287-294 |
6 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
Power-Driven Routing-Constrained Scan Chain Design.
J. Electronic Testing 20(6): 647-660 (2004) |
2003 |
5 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.
ITC 2003: 488-493 |
2002 |
4 | EE | Yannick Bonhomme,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch:
Test Power: a Big Issue in Large SOC Designs.
DELTA 2002: 447-449 |
3 | EE | Yannick Bonhomme,
Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch:
Power Driven Chaining of Flip-Flops in Scan Architectures.
ITC 2002: 796-803 |
2001 |
2 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.
Asian Test Symposium 2001: 253-258 |
1 | EE | Yannick Bonhomme,
Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch:
A Gated Clock Scheme for Low Power Scan-Based BIST.
IOLTW 2001: 87-89 |