Ian G. Harris

2007
32	EE	Shireesh Verma, Ian G. Harris, Kiran Ramineni: Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions. DATE 2007: 900-905
31	EE	Franco Fummi, Cristina Marconcini, Graziano Pravadelli, Ian G. Harris: A CLP-Based Functional ATPG for Extended FSMs. MTV 2007: 98-105
2006
30	EE	Ian G. Harris: A coverage metric for the validation of interacting processes. DATE 2006: 1019-1024
29	EE	Ian G. Harris: Guest Editor's Introduction to the Special Section on Simulation-Based Design Validation. IEEE Trans. Computers 55(11): 1313-1314 (2006)
28	EE	Ian G. Harris, Franco Fummi: Guest Editor's Introduction. International Journal of Parallel Programming 34(1): 1-2 (2006)
2005
27	EE	Shireesh Verma, Kiran Ramineni, Ian G. Harris: An efficient control-oriented coverage metric. ASP-DAC 2005: 317-322
26	EE	Ian G. Harris: Introduction. ACM Trans. Design Autom. Electr. Syst. 10(4): 587-588 (2005)
25	EE	Matthew W. Heath, Wayne P. Burleson, Ian G. Harris: Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test. IEEE Trans. Computers 54(12): 1532-1546 (2005)
24	EE	Franco Fummi, Ian G. Harris: Editorial. International Journal of Parallel Programming 33(6): 583-584 (2005)
2004
23	EE	Matthew W. Heath, Wayne P. Burleson, Ian G. Harris: Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s. DATE 2004: 410-415
22		Carol Stolicny, Tapio Koivukangas, Rubin A. Parekhji, Ian G. Harris, Rob Aitken: ITC 2003 panels: Part 1. IEEE Design & Test of Computers 21(2): 160-163 (2004)
2003
21	EE	Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski: Fast Computation of Data Correlation Using BDDs. DATE 2003: 10122-10129
20	EE	Dereck A. Fernandes, Ian G. Harris: Application of Built in Self-Test for Interconnect Testing of FPGAs. ITC 2003: 1248-1257
19	EE	Ian G. Harris: The Confluence of Manufacturing Test and Design Validation. ITC 2003: 1290
18	EE	Matthew W. Heath, Ian G. Harris: A Deterministic Globally Asynchronous Locally Synchronousy Microprocessor Architecture. MTV 2003: 119-
17	EE	Ian G. Harris: Fault Models and Test Generation for Hardware-Software Covalidation. IEEE Design & Test of Computers 20(4): 40-47 (2003)
16	EE	Qiushuang Zhang, Ian G. Harris: Partial BIST insertion to eliminate data correlation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 374-379 (2003)
15	EE	Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris: ATPG for Timing Errors in Globally Asynchronous Locally Synchronous Systems. Journal of Circuits, Systems, and Computers 12(3): 305-332 (2003)
2002
14	EE	Ian G. Harris, Russell Tessier: Testing and diagnosis of interconnect faults in cluster-based FPGA architectures. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1337-1343 (2002)
2001
13		Qiushuang Zhang, Ian G. Harris: A validation fault model for timing-induced functional errors. ITC 2001: 813-820
12		Ian G. Harris, Premachandran R. Menon, Russell Tessier: BIST-based delay path testing in FPGA architectures. ITC 2001: 932-938
2000
11	EE	Ian G. Harris, Russell Tessier: Interconnect testing in cluster-based FPGA architectures. DAC 2000: 49-54
10		Qiushuang Zhang, Ian G. Harris: A Data Flow Fault Coverage Metric for Validation of Behavioral HDL Descriptions. ICCAD 2000: 369-372
9		Ian G. Harris, Russell Tessier: Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures. ICCAD 2000: 472-475
8		Qiushuang Zhang, Ian G. Harris: A domain coverage metric for the validation of behavioral VHDL descriptions. ITC 2000: 302-308
1999
7	EE	Qiushuang Zhang, Ian G. Harris: Partial BIST insertion to eliminate data correlation. ICCAD 1999: 395-399
1994
6	EE	Ian G. Harris, Alex Orailoglu: Microarchitectural Synthesis of VLSI Designs with High Test Concurrency. DAC 1994: 206-211
5		Ian G. Harris, Alex Orailoglu: Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST. EDAC-ETC-EUROASIC 1994: 119-123
4		Ian G. Harris, Alex Orailoglu: SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability. ICCD 1994: 101-104
1993
3		Alex Orailoglu, Ian G. Harris: Test Path Generation and Test Scheduling for Self-Testable Designs. ICCD 1993: 528-531
2		Ian G. Harris, Alex Orailoglu: Intertwined Scheduling, Module Selection and Allocation in Time-and-Area. ISCAS 1993: 1682-1685
1991
1		P. Venkat Rangan, Walter A. Burkhard, Robert W. Rowdidge, Harrick M. Vin, John W. Lindwall, Kashun Chan, Ingvar A. Aaberg, Linda M. Yamamoto, Ian G. Harris: A Testbed for Managing Digital Video and Audio Storage. USENIX Summer 1991: 199-208

Coauthor Index

1	Ingvar A. Aaberg	[1]
2	Rob Aitken	[22]
3	Srikanth Arekapudi	[15]
4	Walter A. Burkhard	[1]
5	Wayne P. Burleson (Wayne Burleson)	[23] [25]
6	Kashun Chan	[1]
7	Maciej J. Ciesielski	[21]
8	Dereck A. Fernandes	[20]
9	Franco Fummi	[24] [28] [31]
10	Matthew W. Heath	[18] [23] [25]
11	Tapio Koivukangas	[22]
12	John W. Lindwall	[1]
13	Cristina Marconcini	[31]
14	Premachandran R. Menon	[12]
15	Alex Orailoglu	[2] [3] [4] [5] [6]
16	Rubin A. Parekhji	[22]
17	Jinzheng Peng	[15]
18	Graziano Pravadelli	[31]
19	Kiran Ramineni	[27] [32]
20	P. Venkat Rangan	[1]
21	Robert W. Rowdidge	[1]
22	Carol Stolicny	[22]
23	Russell Tessier	[9] [11] [12] [14]
24	Shireesh Verma	[27] [32]
25	Harrick M. Vin	[1]
26	Fei Xin	[15]
27	Linda M. Yamamoto	[1]
28	Zhihong Zeng	[21]
29	Qiushuang Zhang	[7] [8] [10] [13] [16] [21]

Colors in the list of coauthors