| 2008 |
|---|
| 83 | EE | Pouria Bastani,
Kip Killpack,
Li-C. Wang,
Eli Chiprout:
Speedpath prediction based on learning from a small set of examples.
DAC 2008: 217-222 |
| 82 | EE | Onur Guzey,
Li-C. Wang,
Jeremy R. Levitt,
Harry Foster:
Functional test selection based on unsupervised support vector analysis.
DAC 2008: 262-267 |
| 81 | EE | Pouria Bastani,
Nicholas Callegari,
Li-C. Wang,
Magdy S. Abadir:
Statistical diagnosis of unmodeled systematic timing effects.
DAC 2008: 355-360 |
| 2007 |
|---|
| 80 | | Magdy S. Abadir,
Li-C. Wang,
Jayanta Bhadra:
Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA
IEEE Computer Society 2007 |
| 79 | EE | Li-C. Wang,
Pouria Bastani,
Magdy S. Abadir:
Design-Silicon Timing Correlation A Data Mining Perspective.
DAC 2007: 384-389 |
| 78 | EE | Charles H.-P. Wen,
Li-C. Wang,
Jayanta Bhadra:
An incremental learning framework for estimating signal controllability in unit-level verification.
ICCAD 2007: 250-257 |
| 77 | EE | Jayanta Bhadra,
Magdy S. Abadir,
Li-C. Wang:
Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques.
IEEE Design & Test of Computers 24(2): 110-111 (2007) |
| 76 | EE | Jayanta Bhadra,
Magdy S. Abadir,
Li-C. Wang,
Sandip Ray:
A Survey of Hybrid Techniques for Functional Verification.
IEEE Design & Test of Computers 24(2): 112-122 (2007) |
| 2006 |
|---|
| 75 | | Magdy S. Abadir,
Li-C. Wang,
Jayanta Bhadra:
Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA
IEEE Computer Society 2006 |
| 74 | EE | Benjamin N. Lee,
Li-C. Wang,
Magdy S. Abadir:
Refined statistical static timing analysis through.
DAC 2006: 149-154 |
| 73 | EE | Onur Guzey,
Charles H.-P. Wen,
Li-C. Wang,
Tao Feng,
Hillel Miller,
Magdy S. Abadir:
Extracting a Simplified View of Design Functionality Based on Vector Simulation.
Haifa Verification Conference 2006: 34-49 |
| 72 | EE | Leonard Lee,
Li-C. Wang:
On bounding the delay of a critical path.
ICCAD 2006: 81-88 |
| 71 | EE | Charles H.-P. Wen,
Onur Guzey,
Li-C. Wang:
Simulation-based functional test justification using a decision-digram-based Boolean data miner.
ICCD 2006 |
| 70 | EE | Charles H.-P. Wen,
Li-C. Wang,
Kwang-Ting Cheng:
Simulation-Based Functional Test Generation for Embedded Processors.
IEEE Trans. Computers 55(11): 1335-1343 (2006) |
| 2005 |
|---|
| 69 | | Magdy S. Abadir,
Li-C. Wang:
Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA
IEEE Computer Society 2005 |
| 68 | EE | Feng Lu,
Madhu K. Iyer,
Ganapathy Parthasarathy,
Li-C. Wang,
Kwang-Ting Cheng,
Kuang-Chien Chen:
An Efficient Sequential SAT Solver With Improved Search Strategies.
DATE 2005: 1102-1107 |
| 67 | EE | Leonard Lee,
Sean Wu,
Charles H.-P. Wen,
Li-C. Wang:
On Generating Tests to Cover Diverse Worst-Case Timing Corners.
DFT 2005: 415-426 |
| 66 | EE | Charles H.-P. Wen,
Li-C. Wang:
Simulation Data Mining for Functional Test Pattern Justification.
MTV 2005: 76-83 |
| 65 | EE | Charles H.-P. Wen,
Li-C. Wang,
Kwang-Ting Cheng,
Kai Yang,
Wei-Ting Liu,
Ji-Jan Chen:
On A Software-Based Self-Test Methodology and Its Application.
VTS 2005: 107-113 |
| 64 | EE | Benjamin N. Lee,
Li-C. Wang,
Magdy S. Abadir:
Reducing Pattern Delay Variations for Screening Frequency Dependent Defects.
VTS 2005: 153-160 |
| 63 | EE | Leonard Lee,
Li-C. Wang,
Praveen Parvathala,
T. M. Mak:
On Silicon-Based Speed Path Identification.
VTS 2005: 35-41 |
| 62 | EE | Tao Feng,
Li-C. Wang,
Kwang-Ting Cheng,
Chih-Chan Lin:
Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator.
ACM Trans. Design Autom. Electr. Syst. 10(4): 627-650 (2005) |
| 2004 |
|---|
| 61 | EE | Chee-Kian Ong,
Dongwoo Hong,
Kwang-Ting Cheng,
Li-C. Wang:
Jitter spectral extraction for multi-gigahertz signal.
ASP-DAC 2004: 298-303 |
| 60 | EE | Ganapathy Parthasarathy,
Madhu K. Iyer,
Kwang-Ting Cheng,
Li-C. Wang:
Efficient reachability checking using sequential SAT.
ASP-DAC 2004: 418-423 |
| 59 | EE | Tao Feng,
Li-C. Wang,
Kwang-Ting Cheng:
Improved symbolic simulation by functional-space decomposition.
ASP-DAC 2004: 634-639 |
| 58 | EE | Kai Yang,
Kwang-Ting Cheng,
Li-C. Wang:
TranGen: a SAT-based ATPG for path-oriented transition faults.
ASP-DAC 2004: 92-97 |
| 57 | EE | Ganapathy Parthasarathy,
Madhu K. Iyer,
Kwang-Ting Cheng,
Li-C. Wang:
An efficient finite-domain constraint solver for circuits.
DAC 2004: 212-217 |
| 56 | EE | Li-C. Wang,
T. M. Mak,
Kwang-Ting Cheng,
Magdy S. Abadir:
On path-based learning and its applications in delay test and diagnosis.
DAC 2004: 492-497 |
| 55 | EE | Mango Chia-Tso Chao,
Li-C. Wang,
Kwang-Ting Cheng:
Pattern Selection for Testing of Deep Sub-Micron Timing Defects.
DATE 2004: 160 |
| 54 | EE | Chee-Kian Ong,
Dongwoo Hong,
Kwang-Ting Cheng,
Li-C. Wang:
Random Jitter Extraction Technique in a Multi-Gigahertz Signal.
DATE 2004: 286-291 |
| 53 | EE | Tao Feng,
Li-C. Wang,
Kwang-Ting Cheng,
Chih-Chan Lin:
Improved Symoblic Simulation by Dynamic Funtional Space Partitioning.
DATE 2004: 42-49 |
| 52 | EE | Li-C. Wang:
Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation.
DATE 2004: 692-695 |
| 51 | EE | Rob A. Rutenbar,
Li-C. Wang,
Kwang-Ting Cheng,
Sandip Kundu:
Static statistical timing analysis for latch-based pipeline designs.
ICCAD 2004: 468-472 |
| 50 | EE | Leonard Lee,
Li-C. Wang,
T. M. Mak,
Kwang-Ting Cheng:
A path-based methodology for post-silicon timing validation.
ICCAD 2004: 713-720 |
| 49 | EE | Jing Zeng,
Magdy S. Abadir,
A. Kolhatkar,
G. Vandling,
Li-C. Wang,
Jacob A. Abraham:
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
ITC 2004: 31-37 |
| 48 | EE | Jing Zeng,
Magdy S. Abadir,
G. Vandling,
Li-C. Wang,
S. Karako,
Jacob A. Abraham:
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design.
MTV 2004: 103-109 |
| 47 | EE | Chee-Kian Ong,
Dongwoo Hong,
Kwang-Ting Cheng,
Li-C. Wang:
A Scalable On-Chip Jitter Extraction Technique.
VTS 2004: 267-272 |
| 46 | EE | Ganapathy Parthasarathy,
Madhu K. Iyer,
Kwang-Ting Cheng,
Li-C. Wang:
Safety Property Verification Using Sequential SAT and Bounded Model Checking.
IEEE Design & Test of Computers 21(2): 132-143 (2004) |
| 45 | EE | Magdy S. Abadir,
Li-C. Wang:
Guest Editors' Introduction: The Verification and Test of Complex Digital ICs.
IEEE Design & Test of Computers 21(2): 80-82 (2004) |
| 44 | EE | T. M. Mak,
Angela Krstic,
Kwang-Ting (Tim) Cheng,
Li-C. Wang:
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs.
IEEE Design & Test of Computers 21(3): 241-247 (2004) |
| 43 | EE | Li-C. Wang,
Jing-Jia Liou,
Kwang-Ting Cheng:
Critical path selection for delay fault testing based upon a statistical timing model.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(11): 1550-1565 (2004) |
| 42 | EE | Cliff C. N. Sze,
Ting-Chi Wang,
Li-C. Wang:
Multilevel circuit clustering for delay minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1073-1085 (2004) |
| 41 | EE | Feng Lu,
Li-C. Wang,
Kwang-Ting (Tim) Cheng,
John Moondanos,
Ziyad Hanna:
A Signal Correlation Guided Circuit-SAT Solver.
J. UCS 10(12): 1629-1654 (2004) |
| 2003 |
|---|
| 40 | EE | Feng Lu,
Li-C. Wang,
Kwang-Ting Cheng,
John Moondanos,
Ziyad Hanna:
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases.
DAC 2003: 436-441 |
| 39 | EE | Angela Krstic,
Li-C. Wang,
Kwang-Ting Cheng,
Jing-Jia Liou,
T. M. Mak:
Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models.
DAC 2003: 668-673 |
| 38 | EE | Angela Krstic,
Li-C. Wang,
Kwang-Ting Cheng,
Jing-Jia Liou,
Magdy S. Abadir:
Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step.
DATE 2003: 10328-10335 |
| 37 | EE | Feng Lu,
Li-C. Wang,
Kwang-Ting Cheng,
Ric C.-Y. Huang:
A Circuit SAT Solver With Signal Correlation Guided Learning.
DATE 2003: 10892-10897 |
| 36 | EE | Angela Krstic,
Jing-Jia Liou,
Kwang-Ting Cheng,
Li-C. Wang:
On Structural vs. Functional Testing for Delay Faults.
ISQED 2003: 438-441 |
| 35 | EE | Li-C. Wang,
Angela Krstic,
Leonard Lee,
Kwang-Ting Cheng,
M. Ray Mercer,
Thomas W. Williams,
Magdy S. Abadir:
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects.
ITC 2003: 1041-1050 |
| 34 | EE | Angela Krstic,
Li-C. Wang,
Kwang-Ting Cheng,
T. M. Mak:
Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies.
ITC 2003: 339-348 |
| 33 | EE | Angela Krstic,
Li-C. Wang,
Kwang-Ting Cheng,
Jing-Jia Liou:
Diagnosis of Delay Defects Using Statistical Timing Models.
VTS 2003: 339-344 |
| 32 | EE | Kenneth M. Butler,
Kwang-Ting (Tim) Cheng,
Li-C. Wang:
Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs.
IEEE Design & Test of Computers 20(5): 6-7 (2003) |
| 2002 |
|---|
| 31 | EE | Jing-Jia Liou,
Li-C. Wang,
Kwang-Ting Cheng,
Jennifer Dworak,
M. Ray Mercer,
Rohit Kapur,
Thomas W. Williams:
Enhancing test efficiency for delay fault testing using multiple-clocked schemes.
DAC 2002: 371-374 |
| 30 | EE | Jing-Jia Liou,
Angela Krstic,
Li-C. Wang,
Kwang-Ting Cheng:
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation.
DAC 2002: 566-569 |
| 29 | EE | Jennifer Dworak,
James Wingfield,
Brad Cobb,
Sooryong Lee,
Li-C. Wang,
M. Ray Mercer:
Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults.
DFT 2002: 177-185 |
| 28 | EE | Jing-Jia Liou,
Li-C. Wang,
Kwang-Ting Cheng:
On theoretical and practical considerations of path selection for delay fault testing.
ICCAD 2002: 94-100 |
| 27 | EE | Ganapathy Parthasarathy,
Madhu K. Iyer,
Tao Feng,
Li-C. Wang,
Kwang-Ting Cheng,
Magdy S. Abadir:
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems.
ITC 2002: 203-212 |
| 26 | EE | Li-C. Wang,
Magdy S. Abadir,
Juhong Zhu:
On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults.
ITC 2002: 398-406 |
| 25 | EE | Jing-Jia Liou,
Li-C. Wang,
Kwang-Ting Cheng,
Jennifer Dworak,
M. Ray Mercer,
Rohit Kapur,
Thomas W. Williams:
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme.
ITC 2002: 407-416 |
| 2001 |
|---|
| 24 | EE | Jianbang Lai,
Ming-Shiun Lin,
Ting-Chi Wang,
Li-C. Wang:
Module placement with boundary constraints using the sequence-pair representation.
ASP-DAC 2001: 515-520 |
| 23 | EE | Magdy S. Abadir,
Li-C. Wang:
Verification and Validation of Complex Digital Systems: An Industrial Perspective.
ISQED 2001: 11-12 |
| 22 | EE | Magdy S. Abadir,
Juhong Zhu,
Li-C. Wang:
Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor.
VTS 2001: 252-259 |
| 21 | EE | Jennifer Dworak,
Jason D. Wicker,
Sooryong Lee,
Michael R. Grimaila,
M. Ray Mercer,
Kenneth M. Butler,
Bret Stewart,
Li-C. Wang:
Defect-Oriented Testing and Defective-Part-Level Prediction.
IEEE Design & Test of Computers 18(1): 31-41 (2001) |
| 2000 |
|---|
| 20 | EE | Jennifer Dworak,
Michael R. Grimaila,
Brad Cobb,
Ting-Chi Wang,
Li-C. Wang,
M. Ray Mercer:
On the superiority of DO-RE-ME/MPG-D over stuck-at-based defective part level prediction.
Asian Test Symposium 2000: 151- |
| 19 | EE | Kwang-Ting Cheng,
Vishwani D. Agrawal,
Jing-Yang Jou,
Li-C. Wang,
Chi-Feng Wu,
Shianling Wu:
Collaboration between Industry and Academia in Test Research.
Asian Test Symposium 2000: 17- |
| 18 | | Jennifer Dworak,
Michael R. Grimaila,
Sooryong Lee,
Li-C. Wang,
M. Ray Mercer:
Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D.
ITC 2000: 930-939 |
| 17 | EE | Li-C. Wang,
Magdy S. Abadir:
On Efficiently Producing Quality Tests for Custom Circuits in PowerPCTM Microprocessors.
J. Electronic Testing 16(1-2): 121-130 (2000) |
| 1999 |
|---|
| 16 | | Jennifer Dworak,
Michael R. Grimaila,
Sooryong Lee,
Li-C. Wang,
M. Ray Mercer:
Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies.
ITC 1999: 1031-1037 |
| 15 | | Li-C. Wang,
Magdy S. Abadir:
Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors.
ITC 1999: 830-838 |
| 14 | EE | Michael R. Grimaila,
Sooryong Lee,
Jennifer Dworak,
Kenneth M. Butler,
Bret Stewart,
Hari Balachandran,
Bryan Houchins,
Vineet Mathur,
Jaehong Park,
Li-C. Wang,
M. Ray Mercer:
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen.
VTS 1999: 268-274 |
| 13 | EE | Li-C. Wang,
Magdy S. Abadir:
Experience in Validation of PowerPCTM Microprocessor Embedded Arrays.
J. Electronic Testing 15(1-2): 191-205 (1999) |
| 1998 |
|---|
| 12 | EE | Li-C. Wang,
Magdy S. Abadir,
Nari Krishnamurthy:
Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation.
DAC 1998: 534-537 |
| 11 | EE | Li-C. Wang,
Magdy S. Abadir,
Jing Zeng:
Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays.
DATE 1998: 273-277 |
| 10 | EE | Arun Chandra,
Li-C. Wang,
Magdy S. Abadir:
Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors.
Great Lakes Symposium on VLSI 1998: 362-367 |
| 9 | EE | Li-C. Wang,
Magdy S. Abadir,
Jing Zeng:
On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays.
VTS 1998: 260-265 |
| 8 | EE | Li-C. Wang,
Magdy S. Abadir,
Jing Zeng:
On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays.
ACM Trans. Design Autom. Electr. Syst. 3(4): 524-532 (1998) |
| 7 | EE | Li-C. Wang,
Magdy S. Abadir:
Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays.
J. Electronic Testing 13(2): 121-135 (1998) |
| 1997 |
|---|
| 6 | | Li-C. Wang,
Magdy S. Abadir:
A New Validation Methodology Combining Test and Formal Verification for PowerPCTM Microprocessor Arrays.
ITC 1997: 954-963 |
| 1996 |
|---|
| 5 | EE | Li-C. Wang,
M. Ray Mercer,
Thomas W. Williams:
A Better ATPG Algorithm and Its Design Principles.
ICCD 1996: 248-253 |
| 4 | | Li-C. Wang,
M. Ray Mercer,
Thomas W. Williams:
Using Target Faults To Detect Non-Tartget Defects.
ITC 1996: 629-638 |
| 1995 |
|---|
| 3 | | Li-C. Wang,
M. Ray Mercer,
Thomas W. Williams:
On Efficiently and Reliably Achieving Low Defective Part Levels.
ITC 1995: 616-625 |
| 2 | EE | Li-C. Wang,
M. Ray Mercer,
Sophia W. Kao,
Thomas W. Williams:
On the decline of testing efficiency as fault coverage approaches 100%.
VTS 1995: 74-83 |
| 1993 |
|---|
| 1 | EE | Albert G. Greenberg,
Boris D. Lubachevsky,
Li-C. Wang:
Experience in Massively Parallel Discrete Event Simulation.
SPAA 1993: 193-202 |
