2004 |
16 | EE | Jitendra Khare:
Memory Yield Improvement - SoC Design Perspective.
ITC 2004: 1445 |
15 | EE | Hans T. Heineken,
Jitendra Khare:
Test Strategies For a 40Gbps Framer SoC.
ITC 2004: 758-763 |
2003 |
14 | EE | Jitendra Khare:
DFM - A Fabless Perspective.
ITC 2003: 1317 |
2001 |
13 | | John T. Chen,
Jitendra Khare,
Ken Walker,
Saghir A. Shaikh,
Janusz Rajski,
Wojciech Maly:
Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring.
ITC 2001: 258-267 |
12 | EE | John T. Chen,
Wojciech Maly,
Janusz Rajski,
Omar Kebichi,
Jitendra Khare:
Enabling Embedded Memory Diagnosis via Test Response Compression.
VTS 2001: 292-298 |
2000 |
11 | EE | Jitendra Khare,
Hans T. Heineken,
M. d'Abreu:
Cost Trade-Offs in System On Chip Designs.
VLSI Design 2000: 178-184 |
10 | EE | Saghir A. Shaikh,
Jitendra Khare,
Hans T. Heineken:
Manufacturability and Testability Oriented Synthesis.
VLSI Design 2000: 185-191 |
9 | EE | Charles H. Ouyang,
Hans T. Heineken,
Jitendra Khare,
Saghir A. Shaikh,
M. d'Abreu:
Maximizing Wafer Productivity Through Layout Optimization.
VLSI Design 2000: 192-197 |
8 | EE | A. Bommireddy,
Jitendra Khare,
Saghir A. Shaikh,
S.-T. Su:
Test and Debug of Networking SoCs: A Case Study.
VTS 2000: 121-126 |
1998 |
7 | EE | Wojciech Maly,
Pranab K. Nag,
Hans T. Heineken,
Jitendra Khare:
Design-Manufacturing Interface: Part I - Vision.
DATE 1998: 550-556 |
6 | EE | Wojciech Maly,
Pranab K. Nag,
Charles H. Ouyang,
Hans T. Heineken,
Jitendra Khare,
P. Simon:
Design-Manufacturing Interface: Part II - Applications.
DATE 1998: 557-562 |
1997 |
5 | EE | Hans T. Heineken,
Jitendra Khare,
Wojciech Maly,
Pranab K. Nag,
Charles H. Ouyang,
Witold A. Pleskacz:
CAD at the Design-Manufacturing Interface.
DAC 1997: 321-326 |
1996 |
4 | EE | Wojciech Maly,
Hans T. Heineken,
Jitendra Khare,
Pranab K. Nag:
Design for manufacturability in submicron domain.
ICCAD 1996: 690-697 |
3 | EE | Jitendra Khare,
Wojciech Maly,
Nathan Tiday:
Fault characterization of standard cell libraries using inductive contamination.
VTS 1996: 405-413 |
1995 |
2 | | Jitendra Khare,
Wojciech Maly:
Inductive Contamination Analysis (ICA) with SRAM Application.
ITC 1995: 552-560 |
1 | EE | Jitendra Khare,
Sujoy Mitra,
Pranab K. Nag,
U. Maly,
Rob A. Rutenbar:
Testability-oriented channel routing.
VLSI Design 1995: 208-213 |