2008 |
18 | EE | Herman Koppelman,
Harald P. E. Vranken:
Experiences with a synchronous virtual classroom in distance education.
ITiCSE 2008: 194-198 |
2006 |
17 | EE | Harald P. E. Vranken,
Sandeep Kumar Goel,
Andreas Glowatz,
Jürgen Schlöffel,
Friedrich Hapke:
Fault detection and diagnosis with parity trees for space compaction of test responses.
DAC 2006: 1095-1098 |
2004 |
16 | EE | Harald P. E. Vranken,
Ferry Syafei Sapei,
Hans-Joachim Wunderlich:
Impact of Test Point Insertion on Silicon Area and Timing during Layout.
DATE 2004: 810-815 |
15 | EE | Yuyi Tang,
Hans-Joachim Wunderlich,
Harald P. E. Vranken,
Friedrich Hapke,
Michael Wittke,
Piet Engelke,
Ilia Polian,
Bernd Becker:
X-Masking During Logic BIST and Its Impact on Defect Coverage.
ITC 2004: 442-451 |
14 | EE | Valentin Gherman,
Hans-Joachim Wunderlich,
Harald P. E. Vranken,
Friedrich Hapke,
Michael Wittke,
Michael Garbers:
Efficient Pattern Mapping for Deterministic Logic BIST.
ITC 2004: 48-56 |
2003 |
13 | EE | Harald P. E. Vranken,
Friedrich Hapke,
Soenke Rogge,
Domenico Chindamo,
Erik H. Volkerink:
ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume.
ITC 2003: 1069-1078 |
2002 |
12 | EE | Harald P. E. Vranken,
Tom Waayers,
Hérvé Fleury,
David Lelouvier:
Enhanced Reduced Pin-Count Test for Full-Scan Design.
J. Electronic Testing 18(2): 129-143 (2002) |
2001 |
11 | EE | A. Irion,
Gundolf Kiefer,
Harald P. E. Vranken,
Hans-Joachim Wunderlich:
Circuit partitioning for efficient logic BIST synthesis.
DATE 2001: 86-91 |
10 | | Harald P. E. Vranken,
Tom Waayers,
Hérvé Fleury,
David Lelouvier:
Enhanced reduced pin-count test for full-scan design.
ITC 2001: 738-747 |
9 | EE | Gundolf Kiefer,
Harald P. E. Vranken,
Erik Jan Marinissen,
Hans-Joachim Wunderlich:
Application of Deterministic Logic BIST on Industrial Circuits.
J. Electronic Testing 17(3-4): 351-362 (2001) |
2000 |
8 | EE | Harald P. E. Vranken,
Tomás Garciá Garciá,
Sjouke Mauw,
Loe M. G. Feijs:
IC Design Validation Using Message Sequence Charts.
EUROMICRO 2000: 1122- |
7 | EE | Jeroen Voeten,
Harald P. E. Vranken:
Behavior-Preserving Transformations for Design-for-Test.
EUROMICRO 2000: 1193- |
6 | | Gundolf Kiefer,
Hans-Joachim Wunderlich,
Harald P. E. Vranken,
Erik Jan Marinissen:
Application of deterministic logic BIST on industrial circuits.
ITC 2000: 105-114 |
5 | EE | Harald P. E. Vranken:
Debug Facilities in the TriMedia CPU64 Architecture.
J. Electronic Testing 16(3): 301-308 (2000) |
1999 |
4 | EE | Jos T. J. van Eijndhoven,
Kees A. Vissers,
Evert-Jan D. Pol,
P. Struik,
R. H. J. Bloks,
Pieter van der Wolf,
Harald P. E. Vranken,
Frans Sijstermans,
M. J. A. Tromp,
Andy D. Pimentel:
TriMedia CPU64 Architecture.
ICCD 1999: 586-592 |
1997 |
3 | EE | Harald P. E. Vranken,
M. P. J. Stevens,
M. T. M. Segers:
Design-For-Debug in Hardware/Software Co-Design.
CODES 1997: 35-42 |
1996 |
2 | EE | Harald P. E. Vranken,
Marc F. Witteman,
Ronald C. van Wuijtswinkel:
Design for Testability in Hardware-Software Systems.
IEEE Design & Test of Computers 13(3): 79-87 (1996) |
1994 |
1 | | Harald P. E. Vranken,
M. P. J. Stevens,
M. T. M. Segers,
J. H. M. M. van Rhee:
System-Level Testability of Hardware/Software Systems.
ITC 1994: 134-142 |