T. M. Mak

2008
44	EE	Cecilia Metra, Martin Omaña, T. M. Mak, Asifur Rahman, Simon Tam: Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors. DFT 2008: 465-473
2007
43	EE	T. M. Mak: Infant Mortality--The Lesser Known Reliability Issue. IOLTS 2007: 122
42	EE	Ming Zhang, T. M. Mak, James Tschanz, Kee Sup Kim, Norbert Seifert, Davia Lu: Design for Resilience to Soft Errors and Variations. IOLTS 2007: 23-28
41	EE	Rajesh Thirugnanam, Dong Sam Ha, T. M. Mak: Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor. ISVLSI 2007: 153-158
40	EE	Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam: Novel Approach to Clock Fault Testing for High Performance Microprocessors. VTS 2007: 441-446
39	EE	T. M. Mak: The case for power with test. IEEE Design & Test of Computers 24(3): 296 (2007)
38	EE	Cecilia Metra, Daniele Rossi, T. M. Mak: Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?. IEEE Trans. Computers 56(3): 415-428 (2007)
2006
37		Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak: Can Clock Faults be Detected Through Functional Test? DDECS 2006: 168-173
36	EE	Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak: Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. IOLTS 2006: 17-22
35	EE	T. M. Mak, Subhasish Mitra: Should Logic SER be Solved at the Circuit Level? IOLTS 2006: 199
34	EE	T. M. Mak: Test Challenges for 3D Circuits. IOLTS 2006: 79
33	EE	Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak: Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. VLSI Design 2006: 606-612
32	EE	Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim: Soft Error Resilient System Design through Error Correction. VLSI-SoC 2006: 332-337
31	EE	Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng: Test Consideration for Nanometer-Scale CMOS Circuits. IEEE Design & Test of Computers 23(2): 128-136 (2006)
30	EE	T. M. Mak: Is System in Package the Panacea for Integration? IEEE Design & Test of Computers 23(3): 256 (2006)
29	EE	T. M. Mak, Sani R. Nassif: Guest Editors' Introduction: Process Variation and Stochastic Design and Test. IEEE Design & Test of Computers 23(6): 436-437 (2006)
28	EE	Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, N. J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, S. J. Patel: Sequential Element Design With Built-In Soft Error Resilience. IEEE Trans. VLSI Syst. 14(12): 1368-1378 (2006)
2005
27	EE	T. M. Mak: Limitation of structural scan delay test. Asian Test Symposium 2005: 471
26	EE	Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak: The Other Side of the Timing Equation: a Result of Clock Faults. DFT 2005: 169-177
25	EE	T. M. Mak, Subhasish Mitra, Ming Zhang: DFT Assisted Built-In Soft Error Resilience. IOLTS 2005: 69
24	EE	T. M. Mak: Does It Mean Less Testing for Self Calibrating Design?. IOLTS 2005: 99
23	EE	Leonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak: On Silicon-Based Speed Path Identification. VTS 2005: 35-41
2004
22	EE	Cecilia Metra, T. M. Mak, Martin Omaña: Fault secureness need for next generation high performance microprocessor design for testability structures. Conf. Computing Frontiers 2004: 444-450
21	EE	Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir: On path-based learning and its applications in delay test and diagnosis. DAC 2004: 492-497
20	EE	Cecilia Metra, T. M. Mak, Martin Omaña: Are Our Design for Testability Features Fault Secure? DATE 2004: 714-715
19	EE	Leonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng: A path-based methodology for post-silicon timing validation. ICCAD 2004: 713-720
18	EE	Eric F. Weglarz, Kewal K. Saluja, T. M. Mak: Testing of Hard Faults in Simultaneous Multithreaded Processors. IOLTS 2004: 95-100
17	EE	Cecilia Metra, T. M. Mak, Martin Omaña: Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing. ITC 2004: 1223-1231
16	EE	Sandip Kundu, T. M. Mak, Rajesh Galivanche: Trends in manufacturing test methods and their implications. ITC 2004: 679-687
15	EE	Michael Spica, T. M. Mak: Do We Need Anything More Than Single Bit Error Correction (ECC)? MTDT 2004: 111-116
14	EE	Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak: Defect and Error Tolerance in the Presence of Massive Numbers of Defects. IEEE Design & Test of Computers 21(3): 216-227 (2004)
13	EE	T. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang: New Challenges in Delay Testing of Nanometer, Multigigahertz Designs. IEEE Design & Test of Computers 21(3): 241-247 (2004)
12	EE	T. M. Mak, Mike Tripp, Anne Meixner: Testing Gbps Interfaces without a Gigahertz Tester. IEEE Design & Test of Computers 21(4): 278-286 (2004)
11	EE	Cecilia Metra, Stefano Di Francescantonio, T. M. Mak: Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing. IEEE Trans. Computers 53(5): 531-546 (2004)
2003
10	EE	Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak: Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. DAC 2003: 668-673
9	EE	Cecilia Metra, T. M. Mak, Daniele Rossi: Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors. DFT 2003: 63-70
8	EE	Mike Tripp, T. M. Mak, Anne Meixner: Elimination of Traditional Functional Testing of Interface Timings at Intel. ITC 2003: 1014-1022
7	EE	Mike Tripp, T. M. Mak, Anne Meixner: Elimination of Traditional Functional Testing of Interface Timings at Intel. ITC 2003: 1448-1456
6	EE	Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak: Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies. ITC 2003: 339-348
5	EE	Kaushik Roy, T. M. Mak, Kwang-Ting Cheng: Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. VTS 2003: 313-318
2002
4	EE	Cecilia Metra, Stefano Di Francescantonio, T. M. Mak: Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing. ITC 2002: 100-109
2001
3	EE	Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak: Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects. DFT 2001: 357-365
2		Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer: Crosstalk test generation on pseudo industrial circuits: a case study. ITC 2001: 548-557
1998
1	EE	T. M. Mak, Debika Bhattacharya, Cheryl Prunty, Bob Roeder, Nermine Ramadan, Joel Ferguson, Jianlin Yu: Cache RAM inductive fault analysis with fab defect modeling. ITC 1998: 862-871

Coauthor Index

1	Magdy S. Abadir	[21]
2	Maryam Ashouei	[33]
3	Debika Bhattacharya	[1]
4	Melvin A. Breuer	[2] [14]
5	José Manuel Cazeaux	[26] [36] [37]
6	Abhijit Chatterjee	[33]
7	Liang-Chi Chen	[2]
8	Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng)	[5] [6] [10] [13] [19] [21] [31]
9	Vivek De	[33]
10	Joel Ferguson	[1]
11	Stefano Di Francescantonio	[3] [4] [11]
12	Rajesh Galivanche	[16]
13	Sandeep K. Gupta	[2] [14]
14	Dong Sam Ha	[41]
15	Kee Sup Kim	[28] [32] [42]
16	Angela Krstic	[6] [10] [13]
17	Sandip Kundu	[16]
18	Leonard Lee	[19] [23]
19	Jing-Jia Liou	[10]
20	Davia Lu	[42]
21	Anne Meixner	[7] [8] [12]
22	Cecilia Metra	[3] [4] [9] [11] [17] [20] [22] [26] [36] [37] [38] [40] [44]
23	Subhasish Mitra	[25] [28] [32] [35]
24	Sani R. Nassif	[29]
25	Martin Omaña	[17] [20] [22] [26] [36] [37] [40] [44]
26	Praveen Parvathala	[23]
27	S. J. Patel	[28]
28	Cheryl Prunty	[1]
29	Asifur Rahman	[44]
30	Nermine Ramadan	[1]
31	Bruno Riccò	[3]
32	Bob Roeder	[1]
33	Daniele Rossi	[9] [26] [36] [37] [38]
34	Kaushik Roy	[5] [31]
35	Kewal K. Saluja	[18]
36	Norbert Seifert	[28] [32] [42]
37	Naresh R. Shanbhag	[28]
38	Quan Shi	[28]
39	Adit D. Singh	[33]
40	Michael Spica	[15]
41	Simon Tam	[40] [44]
42	Rajesh Thirugnanam	[41]
43	Mike Tripp	[7] [8] [12]
44	James Tschanz	[42]
45	Li-C. Wang	[6] [10] [13] [19] [21] [23]
46	N. J. Wang	[28]
47	Eric F. Weglarz	[18]
48	Jianlin Yu	[1]
49	Ming Zhang	[25] [28] [32] [42]

Colors in the list of coauthors