T. M. Mak

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44EECecilia Metra, Martin Omaña, T. M. Mak, Asifur Rahman, Simon Tam: Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors. DFT 2008: 465-473
43EET. M. Mak: Infant Mortality--The Lesser Known Reliability Issue. IOLTS 2007: 122
42EEMing Zhang, T. M. Mak, James Tschanz, Kee Sup Kim, Norbert Seifert, Davia Lu: Design for Resilience to Soft Errors and Variations. IOLTS 2007: 23-28
41EERajesh Thirugnanam, Dong Sam Ha, T. M. Mak: Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor. ISVLSI 2007: 153-158
40EECecilia Metra, Martin Omaña, T. M. Mak, Simon Tam: Novel Approach to Clock Fault Testing for High Performance Microprocessors. VTS 2007: 441-446
39EET. M. Mak: The case for power with test. IEEE Design & Test of Computers 24(3): 296 (2007)
38EECecilia Metra, Daniele Rossi, T. M. Mak: Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?. IEEE Trans. Computers 56(3): 415-428 (2007)
37 Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak: Can Clock Faults be Detected Through Functional Test? DDECS 2006: 168-173
36EECecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak: Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. IOLTS 2006: 17-22
35EET. M. Mak, Subhasish Mitra: Should Logic SER be Solved at the Circuit Level? IOLTS 2006: 199
34EET. M. Mak: Test Challenges for 3D Circuits. IOLTS 2006: 79
33EEMaryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak: Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. VLSI Design 2006: 606-612
32EESubhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim: Soft Error Resilient System Design through Error Correction. VLSI-SoC 2006: 332-337
31EEKaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng: Test Consideration for Nanometer-Scale CMOS Circuits. IEEE Design & Test of Computers 23(2): 128-136 (2006)
30EET. M. Mak: Is System in Package the Panacea for Integration? IEEE Design & Test of Computers 23(3): 256 (2006)
29EET. M. Mak, Sani R. Nassif: Guest Editors' Introduction: Process Variation and Stochastic Design and Test. IEEE Design & Test of Computers 23(6): 436-437 (2006)
28EEMing Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, N. J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, S. J. Patel: Sequential Element Design With Built-In Soft Error Resilience. IEEE Trans. VLSI Syst. 14(12): 1368-1378 (2006)
27EET. M. Mak: Limitation of structural scan delay test. Asian Test Symposium 2005: 471
26EECecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak: The Other Side of the Timing Equation: a Result of Clock Faults. DFT 2005: 169-177
25EET. M. Mak, Subhasish Mitra, Ming Zhang: DFT Assisted Built-In Soft Error Resilience. IOLTS 2005: 69
24EET. M. Mak: Does It Mean Less Testing for Self Calibrating Design?. IOLTS 2005: 99
23EELeonard Lee, Li-C. Wang, Praveen Parvathala, T. M. Mak: On Silicon-Based Speed Path Identification. VTS 2005: 35-41
22EECecilia Metra, T. M. Mak, Martin Omaña: Fault secureness need for next generation high performance microprocessor design for testability structures. Conf. Computing Frontiers 2004: 444-450
21EELi-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir: On path-based learning and its applications in delay test and diagnosis. DAC 2004: 492-497
20EECecilia Metra, T. M. Mak, Martin Omaña: Are Our Design for Testability Features Fault Secure? DATE 2004: 714-715
19EELeonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng: A path-based methodology for post-silicon timing validation. ICCAD 2004: 713-720
18EEEric F. Weglarz, Kewal K. Saluja, T. M. Mak: Testing of Hard Faults in Simultaneous Multithreaded Processors. IOLTS 2004: 95-100
17EECecilia Metra, T. M. Mak, Martin Omaña: Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing. ITC 2004: 1223-1231
16EESandip Kundu, T. M. Mak, Rajesh Galivanche: Trends in manufacturing test methods and their implications. ITC 2004: 679-687
15EEMichael Spica, T. M. Mak: Do We Need Anything More Than Single Bit Error Correction (ECC)? MTDT 2004: 111-116
14EEMelvin A. Breuer, Sandeep K. Gupta, T. M. Mak: Defect and Error Tolerance in the Presence of Massive Numbers of Defects. IEEE Design & Test of Computers 21(3): 216-227 (2004)
13EET. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang: New Challenges in Delay Testing of Nanometer, Multigigahertz Designs. IEEE Design & Test of Computers 21(3): 241-247 (2004)
12EET. M. Mak, Mike Tripp, Anne Meixner: Testing Gbps Interfaces without a Gigahertz Tester. IEEE Design & Test of Computers 21(4): 278-286 (2004)
11EECecilia Metra, Stefano Di Francescantonio, T. M. Mak: Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing. IEEE Trans. Computers 53(5): 531-546 (2004)
10EEAngela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak: Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. DAC 2003: 668-673
9EECecilia Metra, T. M. Mak, Daniele Rossi: Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors. DFT 2003: 63-70
8EEMike Tripp, T. M. Mak, Anne Meixner: Elimination of Traditional Functional Testing of Interface Timings at Intel. ITC 2003: 1014-1022
7EEMike Tripp, T. M. Mak, Anne Meixner: Elimination of Traditional Functional Testing of Interface Timings at Intel. ITC 2003: 1448-1456
6EEAngela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak: Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies. ITC 2003: 339-348
5EEKaushik Roy, T. M. Mak, Kwang-Ting Cheng: Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits. VTS 2003: 313-318
4EECecilia Metra, Stefano Di Francescantonio, T. M. Mak: Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing. ITC 2002: 100-109
3EECecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak: Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects. DFT 2001: 357-365
2 Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer: Crosstalk test generation on pseudo industrial circuits: a case study. ITC 2001: 548-557
1EET. M. Mak, Debika Bhattacharya, Cheryl Prunty, Bob Roeder, Nermine Ramadan, Joel Ferguson, Jianlin Yu: Cache RAM inductive fault analysis with fab defect modeling. ITC 1998: 862-871

Coauthor Index

1Magdy S. Abadir [21]
2Maryam Ashouei [33]
3Debika Bhattacharya [1]
4Melvin A. Breuer [2] [14]
5José Manuel Cazeaux [26] [36] [37]
6Abhijit Chatterjee [33]
7Liang-Chi Chen [2]
8Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng) [5] [6] [10] [13] [19] [21] [31]
9Vivek De [33]
10Joel Ferguson [1]
11Stefano Di Francescantonio [3] [4] [11]
12Rajesh Galivanche [16]
13Sandeep K. Gupta [2] [14]
14Dong Sam Ha [41]
15Kee Sup Kim [28] [32] [42]
16Angela Krstic [6] [10] [13]
17Sandip Kundu [16]
18Leonard Lee [19] [23]
19Jing-Jia Liou [10]
20Davia Lu [42]
21Anne Meixner [7] [8] [12]
22Cecilia Metra [3] [4] [9] [11] [17] [20] [22] [26] [36] [37] [38] [40] [44]
23Subhasish Mitra [25] [28] [32] [35]
24Sani R. Nassif [29]
25Martin Omaña [17] [20] [22] [26] [36] [37] [40] [44]
26Praveen Parvathala [23]
27S. J. Patel [28]
28Cheryl Prunty [1]
29Asifur Rahman [44]
30Nermine Ramadan [1]
31Bruno Riccò [3]
32Bob Roeder [1]
33Daniele Rossi [9] [26] [36] [37] [38]
34Kaushik Roy [5] [31]
35Kewal K. Saluja [18]
36Norbert Seifert [28] [32] [42]
37Naresh R. Shanbhag [28]
38Quan Shi [28]
39Adit D. Singh [33]
40Michael Spica [15]
41Simon Tam [40] [44]
42Rajesh Thirugnanam [41]
43Mike Tripp [7] [8] [12]
44James Tschanz [42]
45Li-C. Wang [6] [10] [13] [19] [21] [23]
46N. J. Wang [28]
47Eric F. Weglarz [18]
48Jianlin Yu [1]
49Ming Zhang [25] [28] [32] [42]

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Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)