2008 |
31 | | Vijaykrishnan Narayanan,
C. P. Ravikumar,
Jörg Henkel,
Ali Keshavarzi,
Vojin G. Oklobdzija,
Barry M. Pangrle:
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008
ACM 2008 |
2007 |
30 | | Diana Marculescu,
Anand Raghunathan,
Ali Keshavarzi,
Vijaykrishnan Narayanan:
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007
ACM 2007 |
29 | EE | José Luis Rosselló,
Vicens Canals,
Sebastià A. Bota,
Ali Keshavarzi,
Jaume Segura:
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs
CoRR abs/0710.4759: (2007) |
2006 |
28 | EE | Sebastià A. Bota,
José Luis Rosselló,
Carol de Benito,
Ali Keshavarzi,
Jaume Segura:
Impact of Thermal Gradients on Clock Skew and Testing.
IEEE Design & Test of Computers 23(5): 414-424 (2006) |
2005 |
27 | EE | José Luis Rosselló,
Vicens Canals,
Sebastià A. Bota,
Ali Keshavarzi,
Jaume Segura:
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs.
DATE 2005: 206-211 |
26 | EE | James Tschanz,
Siva Narendra,
Ali Keshavarzi,
Vivek De:
Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power.
ISCAS (1) 2005: 9-12 |
25 | EE | Ali Keshavarzi,
Gerhard Schrom,
Stephen Tang,
Sean Ma,
Keith A. Bowman,
Sunit Tyagi,
Kevin Zhang,
Tom Linton,
Nagib Hakim,
Steven G. Duvall,
John Brews,
Vivek De:
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage.
ISLPED 2005: 26-29 |
24 | EE | Abhijit Chatterjee,
Ali Keshavarzi,
Amit Patra,
Siddhartha Mukhopadhyay:
Test Methodologies in the Deep Submicron Era -- Analog, Mixed-Signal, and RF.
VLSI Design 2005: 12-13 |
2004 |
23 | EE | Arman Vassighi,
Ali Keshavarzi,
Siva Narendra,
Gerhard Schrom,
Yibin Ye,
Seri Lee,
Greg Chrysler,
Manoj Sachdev,
Vivek De:
Design optimizations for microprocessors at low temperature.
DAC 2004: 2-5 |
22 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ali Keshavarzi:
A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs.
ITC 2004: 1108-1117 |
21 | EE | Sebastià A. Bota,
M. Rosales,
José Luis Rosselló,
Jaume Segura,
Ali Keshavarzi:
Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism.
ITC 2004: 1276-1284 |
20 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ali Keshavarzi:
DFT for Delay Fault Testing of High-Performance Digital Circuits.
IEEE Design & Test of Computers 21(3): 248-258 (2004) |
2003 |
19 | EE | Shekhar Borkar,
Tanay Karnik,
Siva Narendra,
James Tschanz,
Ali Keshavarzi,
Vivek De:
Parameter variations and impact on circuits and microarchitecture.
DAC 2003: 338-342 |
18 | EE | Charles F. Hawkins,
Ali Keshavarzi,
Jaume Segura:
A View from the Bottom: Nanometer Technology AC Parametric Failures -- Why, Where, and How to Detect.
DFT 2003: 267- |
17 | EE | Arman Vassighi,
Oleg Semenov,
Manoj Sachdev,
Ali Keshavarzi:
Thermal Management of High Performance Microprocessors.
DFT 2003: 313-319 |
16 | EE | B. Alorda,
B. Bloechel,
Ali Keshavarzi,
Jaume Segura:
CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing.
ITC 2003: 719-726 |
15 | EE | Oleg Semenov,
Arman Vassighi,
Manoj Sachdev,
Ali Keshavarzi,
Charles F. Hawkins:
Burn-in Temperature Projections for Deep Sub-micron Technologies.
ITC 2003: 95-104 |
14 | EE | Ali Keshavarzi,
Kaushik Roy,
Charles F. Hawkins,
Vivek De:
Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ.
IEEE Trans. VLSI Syst. 11(5): 863-870 (2003) |
2002 |
13 | EE | Arman Vassighi,
Oleg Semenov,
Manoj Sachdev,
Ali Keshavarzi:
Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI.
DFT 2002: 12-19 |
12 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ali Keshavarzi:
A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits.
ITC 2002: 1130-1139 |
11 | EE | Jaume Segura,
Ali Keshavarzi,
Jerry M. Soden,
Charles F. Hawkins:
Parametric Failures in CMOS ICs - A Defect-Based Analysis.
ITC 2002: 90-99 |
10 | EE | Jaume Segura,
Vivek De,
Ali Keshavarzi:
Challenges in Nanometric Technology Scaling: Trends and Projections.
VTS 2002: 447-448 |
9 | EE | Zhanping Chen,
Liqiong Wei,
Ali Keshavarzi,
Kaushik Roy:
IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions.
IEEE Design & Test of Computers 19(2): 24-33 (2002) |
8 | EE | Ali Keshavarzi,
James Tschanz,
Siva Narendra,
Vivek De,
W. Robert Daasch,
Kaushik Roy,
Manoj Sachdev,
Charles F. Hawkins:
Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits.
IEEE Design & Test of Computers 19(5): 36-43 (2002) |
7 | EE | Fatih Hamzaoglu,
Yibin Ye,
Ali Keshavarzi,
Kevin Zhang,
Siva Narendra,
Shekhar Borkar,
Mircea R. Stan,
Vivek De:
Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.
IEEE Trans. VLSI Syst. 10(2): 91-95 (2002) |
2001 |
6 | EE | Ali Keshavarzi,
Sean Ma,
Siva Narendra,
B. Bloechel,
K. Mistry,
T. Ghani,
Shekhar Borkar,
Vivek De:
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs.
ISLPED 2001: 207-212 |
5 | EE | Kaushik Roy,
Ali Keshavarzi:
Design and Test of Low Voltage CMOS Circuits.
ISQED 2001: 7 |
2000 |
4 | | Ali Keshavarzi,
Kaushik Roy,
Charles F. Hawkins,
Manoj Sachdev,
K. Soumyanath,
Vivek De:
Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ.
ITC 2000: 1051-1059 |
3 | EE | Ali Keshavarzi,
Kaushik Roy,
Charles F. Hawkins:
Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions.
IEEE Trans. VLSI Syst. 8(6): 717-723 (2000) |
1999 |
2 | EE | Ali Keshavarzi,
Siva Narendra,
Shekhar Borkar,
Charles F. Hawkins,
Kaushik Roy,
Vivek De:
Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's.
ISLPED 1999: 252-254 |
1997 |
1 | | Ali Keshavarzi,
Kaushik Roy,
Charles F. Hawkins:
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs.
ITC 1997: 146-155 |