2007 |
27 | EE | Peter Wohl,
John A. Waicukauski,
Sanjay Patel:
Automated Design and Insertion of Optimal One-Hot Bus Encoders.
VTS 2007: 409-415 |
26 | EE | Peter Wohl,
John A. Waicukauski,
Rohit Kapur,
S. Ramnath,
Emil Gizdarski,
Thomas W. Williams,
P. Jaini:
Minimizing the Impact of Scan Compression.
VTS 2007: 67-74 |
2005 |
25 | EE | Peter Wohl,
John A. Waicukauski,
Sanjay Patel,
Cy Hay,
Emil Gizdarski,
Ben Mathew:
Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST.
VTS 2005: 359-365 |
2004 |
24 | EE | Peter Wohl,
John A. Waicukauski,
Sanjay Patel:
Scalable selector architecture for x-tolerant deterministic BIST.
DAC 2004: 934-939 |
2003 |
23 | EE | Peter Wohl,
John A. Waicukauski,
Sanjay Patel,
Minesh B. Amin:
Efficient compression and application of deterministic patterns in a logic BIST architecture.
DAC 2003: 566-569 |
22 | EE | Peter Wohl,
John A. Waicukauski,
Sanjay Patel,
Minesh B. Amin:
X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture.
ITC 2003: 727-736 |
2002 |
21 | EE | Peter Wohl,
John A. Waicukauski,
Sanjay Patel,
Gregory A. Maston:
Effective diagnostics through interval unloads in a BIST environment.
DAC 2002: 249-254 |
20 | EE | Vishal Jain,
John A. Waicukauski:
Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique.
ITC 2002: 148-153 |
2001 |
19 | | Peter Wohl,
John A. Waicukauski,
Thomas W. Williams:
Design of compactors for signature-analyzers in built-in self-test.
ITC 2001: 54-63 |
2000 |
18 | | Peter Wohl,
John A. Waicukauski:
Optimizing the flattened test-generation model for very large designs.
ITC 2000: 681-690 |
1999 |
17 | | Peter Wohl,
John A. Waicukauski:
Using Verilog simulation libraries for ATPG.
ITC 1999: 1011-1020 |
1998 |
16 | EE | Peter Wohl,
John A. Waicukauski:
Extracting gate-level networks from simulation tables.
ITC 1998: 622-631 |
15 | EE | Peter Wohl,
John A. Waicukauski:
Defining ATPG rules checking in STIL.
ITC 1998: 971-979 |
1997 |
14 | | Peter Wohl,
John A. Waicukauski:
A Unified Interface for Scan Test Generation Based on STIL.
ITC 1997: 1011-1019 |
13 | EE | Peter Wohl,
John A. Waicukauski:
Using ATPG for clock rules checking in complex scan design.
VTS 1997: 130-136 |
1996 |
12 | | Peter Wohl,
John A. Waicukauski:
Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates.
ITC 1996: 13-20 |
11 | | Bejoy G. Oomman,
Wu-Tung Cheng,
John A. Waicukauski:
A Universal Technique for Accelerating Simulation of Scan Test Patterns.
ITC 1996: 135-141 |
10 | | Nadime Zacharia,
Janusz Rajski,
Jerzy Tyszer,
John A. Waicukauski:
Two-Dimensional Test Data Decompressor for Multiple Scan Designs.
ITC 1996: 186-194 |
9 | EE | Peter Wohl,
John A. Waicukauski,
Matthew Graf:
Testing "untestable" faults in three-state circuits.
VTS 1996: 324-331 |
1990 |
8 | EE | Vijay S. Iyengar,
Barry K. Rosen,
John A. Waicukauski:
On computing the sizes of detected delay faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(3): 299-312 (1990) |
1989 |
7 | | John A. Waicukauski,
Eric Lindbloom,
Edward B. Eichelberger,
Orazio P. Forlenza:
A Method for Generating Weighted Random Test Patterns.
IBM Journal of Research and Development 33(2): 149-161 (1989) |
1988 |
6 | | Miron Abramovici,
B. Krishnamurthy,
A. Mathews,
B. Rogers,
M. Schulz,
S. Seth,
John A. Waicukauski:
What is the Path to Fast Fault Simulation?
ITC 1988: 183-192 |
5 | | John A. Waicukauski,
Eric Lindbloom:
Fault Detection Effectiveness of Weighted Random Patterns.
ITC 1988: 245-255 |
1986 |
4 | | John A. Waicukauski,
Eric Lindbloom,
Vijay S. Iyengar,
Barry K. Rosen:
Transition Fault Simulation by Parallel Pattern Single Fault Propagation.
ITC 1986: 542-551 |
1985 |
3 | | John A. Waicukauski,
Eric Lindbloom,
Edward B. Eichelberger,
Donato O. Forlenza,
Tim McCarthy:
A Statistical Calculation of Fault Detection Probabilities By Fast Fault Simulation.
ITC 1985: 779-784 |
1983 |
2 | | Franco Motika,
John A. Waicukauski,
Edward B. Eichelberger,
Eric Lindbloom:
An LSSD Pseudo Random Pattern Test System.
ITC 1983: 283-288 |
1981 |
1 | | Y. Arzoumanian,
John A. Waicukauski:
Fault Diagnosis in an LSSD Environment.
ITC 1981: 86-88 |