| 2003 |
|---|
| 4 | EE | Thomas P. Warwick:
Mitigating the Effects of The DUT Interface board and Test System Parasitics in Gigabit-Plus Measurements.
ITC 2003: 537-544 |
| 2002 |
|---|
| 3 | EE | Thomas P. Warwick:
What a Device Interface Board Really Costs: An Evaluation of Technical Considerations for Testing Products Operating in the Gigabit Region.
ITC 2002: 555-564 |
| 1999 |
|---|
| 2 | | Clifford B. Cole,
Thomas P. Warwick:
High speed digital transceivers: A challenge for manufacturing.
ITC 1999: 211-215 |
| 1 | | Thomas P. Warwick,
Jung Cho,
Yi Cai,
Bill Ortner:
An accurate simulation model of the ATE test environment for very high speed devices.
ITC 1999: 524-531 |
