| 2008 |
|---|
| 66 | EE | Adit D. Singh:
Scan Delay Testing of Nanometer SoCs.
VLSI Design 2008: 13 |
| 65 | EE | Maryam Ashouei,
Adit D. Singh,
Abhijit Chatterjee:
Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS.
VLSI Design 2008: 27-32 |
| 2007 |
|---|
| 64 | EE | Maryam Ashouei,
Muhammad Mudassar Nisar,
Abhijit Chatterjee,
Adit D. Singh,
Abdulkadir Utku Diril:
Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations.
VLSI Design 2007: 711-716 |
| 63 | EE | Gefu Xu,
Adit D. Singh:
Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing.
VLSI Design 2007: 763-768 |
| 2006 |
|---|
| 62 | EE | Gefu Xu,
Adit D. Singh:
Low Cost Launch-on-Shift Delay Test with Slow Scan Enable.
European Test Symposium 2006: 9-14 |
| 61 | EE | Maryam Ashouei,
Abhijit Chatterjee,
Adit D. Singh,
Vivek De,
T. M. Mak:
Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design.
VLSI Design 2006: 606-612 |
| 60 | EE | Adit D. Singh,
Gefu Xu:
Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing.
VTS 2006: 349-357 |
| 59 | EE | Thomas S. Barnett,
Matt Grady,
Kathleen G. Purdy,
Adit D. Singh:
Combining Negative Binomial and Weibull Distributions for Yield and Reliability Prediction.
IEEE Design & Test of Computers 23(2): 110-116 (2006) |
| 58 | EE | Haihua Yan,
Adit D. Singh:
A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI).
IEEE Trans. VLSI Syst. 14(11): 1216-1226 (2006) |
| 57 | EE | Yuvraj Singh Dhillon,
Abdulkadir Utku Diril,
Abhijit Chatterjee,
Adit D. Singh:
Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance.
IEEE Trans. VLSI Syst. 14(5): 514-524 (2006) |
| 56 | EE | Bashir M. Al-Hashimi,
Dimitris Gizopoulos,
Manoj Sachdev,
Adit D. Singh:
New JETTA Editors, 2006.
J. Electronic Testing 22(1): 9-10 (2006) |
| 55 | EE | Xiangdong Xuan,
Adit D. Singh,
Abhijit Chatterjee:
Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects.
J. Electronic Testing 22(4-6): 471-482 (2006) |
| 2005 |
|---|
| 54 | EE | Abdulkadir Utku Diril,
Yuvraj Singh Dhillon,
Abhijit Chatterjee,
Adit D. Singh:
Low-power domino circuits using NMOS pull-up on off-critical paths.
ASP-DAC 2005: 533-538 |
| 53 | EE | Haihua Yan,
Adit D. Singh,
Gefu Xu:
Delay Defect Characterization Using Low Voltage Test.
Asian Test Symposium 2005: 8-13 |
| 52 | EE | Adit D. Singh:
T2: Statistical Methods for VLSI Test and Burn-in Optimization.
Asian Test Symposium 2005 |
| 51 | EE | Maryam Ashouei,
Abhijit Chatterjee,
Adit D. Singh,
Vivek De:
A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS.
ICCD 2005: 567-573 |
| 50 | EE | Haihua Yan,
Gefu Xu,
Adit D. Singh:
Low Voltage Test in Place of Fast Clock in DDSI Delay Test.
ISQED 2005: 316-320 |
| 49 | EE | Abdulkadir Utku Diril,
Yuvraj Singh Dhillon,
Abhijit Chatterjee,
Adit D. Singh:
Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages.
VLSI Design 2005: 159-164 |
| 48 | EE | Haihua Yan,
Adit D. Singh:
A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects.
VLSI Design 2005: 47-52 |
| 47 | EE | Abdulkadir Utku Diril,
Yuvraj Singh Dhillon,
Abhijit Chatterjee,
Adit D. Singh:
Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance.
VTS 2005: 298-303 |
| 46 | EE | Abdulkadir Utku Diril,
Yuvraj Singh Dhillon,
Abhijit Chatterjee,
Adit D. Singh:
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages.
IEEE Trans. VLSI Syst. 13(9): 1103-1107 (2005) |
| 45 | EE | Abdulkadir Utku Diril,
Yuvraj Singh Dhillon,
Abhijit Chatterjee,
Adit D. Singh:
Pseudo Dual Supply Voltage Domino Logic Design.
J. Low Power Electronics 1(2): 145-152 (2005) |
| 2004 |
|---|
| 44 | EE | Haihua Yan,
Adit D. Singh:
Reduce Yield Loss in Delay Defect Detection in Slack Interval.
Asian Test Symposium 2004: 372-377 |
| 43 | EE | Yuvraj Singh Dhillon,
Abdulkadir Utku Diril,
Abhijit Chatterjee,
Adit D. Singh:
Sizing CMOS Circuits for Increased Transient Error Tolerance.
IOLTS 2004: 11-16 |
| 42 | EE | Haihua Yan,
Adit D. Singh:
Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study.
ITC 2004: 242-251 |
| 41 | EE | Yuvraj Singh Dhillon,
Abdulkadir Utku Diril,
Abhijit Chatterjee,
Adit D. Singh:
Low-power dual Vth pseudo dual Vdd domino circuits.
SBCCI 2004: 273-277 |
| 2003 |
|---|
| 40 | EE | Xiangdong Xuan,
Abhijit Chatterjee,
Adit D. Singh,
Namsoo P. Kim,
Mark T. Chisa:
IC Reliability Simulator ARET and Its Application in Design-for-Reliability.
Asian Test Symposium 2003: 18-23 |
| 39 | EE | Adit D. Singh:
Integrating Yield, Test and Reliability: "Statistical Models with Applications to Test and Burn-in Optimization".
ISQED 2003: 7 |
| 38 | EE | Haihua Yan,
Adit D. Singh:
Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die.
ITC 2003: 105-111 |
| 37 | EE | Adit D. Singh:
Should Nanometer Circuits be Periodically Tested in the Field?.
ITC 2003: 1280 |
| 36 | EE | Thomas S. Barnett,
Adit D. Singh:
Relating Yield Models to Burn-In Fall-Out in Time.
ITC 2003: 77-84 |
| 35 | EE | Adit D. Singh,
Markus Seuring,
Michael Gössel,
Egor S. Sogomonyan:
Multimode scan: Test per clock BIST for IP cores.
ACM Trans. Design Autom. Electr. Syst. 8(4): 491-505 (2003) |
| 34 | EE | Thomas S. Barnett,
Adit D. Singh,
Victor P. Nelson:
Extending integrated-circuit yield-models to estimate early-life reliability.
IEEE Transactions on Reliability 52(3): 296-300 (2003) |
| 2002 |
|---|
| 33 | EE | Thomas S. Barnett,
Matt Grady,
Kathleen G. Purdy,
Adit D. Singh:
Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model.
ITC 2002: 693-699 |
| 32 | EE | Michael Gössel,
Egor S. Sogomonyan,
Adit D. Singh:
Scan-Path with Directly Duplicated and Inverted Duplicated Registers.
VTS 2002: 47-52 |
| 31 | EE | Thomas S. Barnett,
Adit D. Singh,
Matt Grady,
Kathleen G. Purdy:
Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction.
VTS 2002: 75-80 |
| 2001 |
|---|
| 30 | EE | Thomas S. Barnett,
Adit D. Singh,
Victor P. Nelson:
Yield-Reliability Modeling for Fault Tolerant Integrated Circuits.
DFT 2001: 29-38 |
| 29 | | Thomas S. Barnett,
Adit D. Singh,
Victor P. Nelson:
Estimating burn-in fall-out for redundant memory.
ITC 2001: 340-347 |
| 28 | EE | Egor S. Sogomonyan,
A. A. Morosov,
Jan Rzeha,
Michael Gössel,
Adit D. Singh:
Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging.
VTS 2001: 184-189 |
| 27 | EE | Thomas S. Barnett,
Adit D. Singh,
Victor P. Nelson:
Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model.
VTS 2001: 326-332 |
| 1999 |
|---|
| 26 | | David R. Lakin II,
Adit D. Singh:
Exploiting defect clustering to screen bare die for infant mortality failures: an experimental study.
ITC 1999: 23-30 |
| 25 | | Adit D. Singh,
Egor S. Sogomonyan,
Michael Gössel,
Markus Seuring:
Testability evaluation of sequential designs incorporating the multi-mode scannable memory element.
ITC 1999: 286-293 |
| 24 | EE | Egor S. Sogomonyan,
Adit D. Singh,
Michael Gössel:
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing.
J. Electronic Testing 15(1-2): 87-96 (1999) |
| 1998 |
|---|
| 23 | EE | Adit D. Singh,
David R. Lakin II,
Gaurav Sinha,
Phil Nigh:
Binning for IC Quality: Experimental Studies on the SEMATECH Data.
DFT 1998: 4-10 |
| 22 | EE | Egor S. Sogomonyan,
Adit D. Singh,
Michael Gössel:
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing.
VTS 1998: 324-331 |
| 1997 |
|---|
| 21 | EE | Christopher G. Knight,
Adit D. Singh,
Victor P. Nelson:
An IDDQ Sensor for Concurrent Timing Error Detection.
DFT 1997: 281-289 |
| 20 | | Adit D. Singh,
Phil Nigh,
C. Mani Krishna:
Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study.
ITC 1997: 362-369 |
| 19 | EE | Walter W. Weber,
Adit D. Singh:
Incorporating IDDQ Testing with BIST for Improved Coverage: An Experimental Study.
J. Electronic Testing 11(2): 147-156 (1997) |
| 1996 |
|---|
| 18 | | Adit D. Singh,
C. Mani Krishna:
On the Effect of Defect Clustering on Test Transparency and IC Test Optimization.
IEEE Trans. Computers 45(6): 753-757 (1996) |
| 1995 |
|---|
| 17 | | Adit D. Singh,
Haroon Rasheed,
Walter W. Weber:
IDDQ Testing of CMOS Opens: An Experimental Study.
ITC 1995: 479-489 |
| 16 | EE | Jason P. Hurst,
Adit D. Singh:
A differential built-in current sensor design for high speed IDDQ testing.
VLSI Design 1995: 419-423 |
| 15 | EE | Walter W. Weber,
Adit D. Singh:
An experimental evaluation of the differential BICS for I/sub DDQ/ testing.
VTS 1995: 472-485 |
| 14 | | Jae Young Lee,
Hee Yong Youn,
Adit D. Singh:
Adaptive Unanimous Voting (UV) Scheme for Distributed Self-Diagnosis.
IEEE Trans. Computers 44(5): 730-735 (1995) |
| 1993 |
|---|
| 13 | | Jae Young Lee,
Hee Yong Youn,
Adit D. Singh:
Adaptive Voting for Faulty (VFF) Node Scheme for Distributed Self-Diagnosis.
FTCS 1993: 480-489 |
| 12 | EE | Adit D. Singh,
C. Mani Krishna:
On optimizing VLSI testing for product quality using die-yield prediction.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(5): 695-709 (1993) |
| 1992 |
|---|
| 11 | | Adit D. Singh,
C. Mani Krishna:
Chip Test Optimization Using Defect Clustering Information.
FTCS 1992: 366-373 |
| 1991 |
|---|
| 10 | | Adit D. Singh,
C. Mani Krishna:
On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield Prediction.
ITC 1991: 228-237 |
| 9 | | Adit D. Singh,
Hee Yong Youn:
A Modular Fault-Tolerant Binary Tree Architecture with Short Links.
IEEE Trans. Computers 40(7): 882-890 (1991) |
| 1990 |
|---|
| 8 | | Adit D. Singh,
Singaravel Murugesan:
Fault-Tolerant Systems - Guest Editors' Introduction to the Special Issue.
IEEE Computer 23(7): 15-17 (1990) |
| 7 | | Israel Koren,
Adit D. Singh:
Fault Tolerance in VLSI Circuits.
IEEE Computer 23(7): 73-83 (1990) |
| 1989 |
|---|
| 6 | | Hee Yong Youn,
Adit D. Singh:
A Near Optimal Adaptive Row Modular Design for Efficiently Reconfiguring the Processor Array in VLSI.
ICPP (1) 1989: 261-265 |
| 5 | | Hee Yong Youn,
Adit D. Singh:
On Implementing Large Binary Tree Architectures in VLSI and WSI.
IEEE Trans. Computers 38(4): 526-537 (1989) |
| 1988 |
|---|
| 4 | | Hee Yong Youn,
Adit D. Singh:
Near Optimal Embedding of Binary Tree Architecture in VLSI.
ICDCS 1988: 86-93 |
| 3 | | Hee Yong Youn,
Adit D. Singh:
A Highly Efficient Design for Reconfiguring the Processor Array in VLSI.
ICPP (1) 1988: 375-382 |
| 2 | | Adit D. Singh:
Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays.
IEEE Trans. Computers 37(11): 1398-1410 (1988) |
| 1987 |
|---|
| 1 | | Hee Yong Youn,
Adit D. Singh:
On Area Efficient and Fault Tolerant Tree Embedding In VLSI.
ICPP 1987: 170-177 |
