| 2006 |
|---|
| 10 | EE | Zhen Shi,
Peter Sandborn:
Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic System Assembly.
J. Electronic Testing 22(1): 49-60 (2006) |
| 2003 |
|---|
| 9 | EE | Zhen Shi,
Peter Sandborn:
Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic Systems Assembly Using Real-Coded Genetic Algorithms.
ITC 2003: 937-946 |
| 2002 |
|---|
| 8 | EE | Daniel Ragan,
Peter Sandborn,
Paul Stoaks:
A detailed cost model for concurrent use with hardware/software co-design.
DAC 2002: 269-274 |
| 2001 |
|---|
| 7 | | Thiagarajan Trichy,
Peter Sandborn,
Ravi Raghavan,
Shubhada Sahasrabudhe:
A new test/diagnosis/rework model for use in technical cost modeling of electronic systems assembly.
ITC 2001: 1108-1117 |
| 6 | EE | Bharatwaj Ramakrishnan,
Peter Sandborn,
Michael G. Pecht:
Process capability indices and product reliability.
Microelectronics Reliability 41(12): 2067-2070 (2001) |
| 1998 |
|---|
| 5 | EE | Peter Sandborn,
Mike Vertal:
Analyzing Packaging Trade-Offs During System Design.
IEEE Design & Test of Computers 15(3): 10-19 (1998) |
| 1997 |
|---|
| 4 | EE | Cynthia F. Murphy,
Magdy S. Abadir,
Peter Sandborn:
Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die.
J. Electronic Testing 10(1-2): 151-166 (1997) |
| 1994 |
|---|
| 3 | EE | Magdy S. Abadir,
Ashish R. Parikh,
Linda Bal,
Peter Sandborn,
Ken Drake:
Analyzing Multichip Module Testing Strategies.
IEEE Design & Test of Computers 11(1): 40-52 (1994) |
| 2 | EE | Magdy S. Abadir,
Ashish Parikh,
Linda Bal,
Peter Sandborn,
Cynthia Murphy:
High Level Test Economics Advisor (Hi-TEA).
J. Electronic Testing 5(2-3): 195-206 (1994) |
| 1 | EE | Peter Sandborn,
Rajarshi Ghosh,
Ken Drake,
Magdy S. Abadir,
Linda Bal,
Ashish Parikh:
Multichip systems trade-off analysis tool.
J. Electronic Testing 5(2-3): 207-218 (1994) |
