Christian Landrault

2008
71	EE	Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Improving Diagnosis Resolution without Physical Information. DELTA 2008: 210-215
70	EE	Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Using TMR Architectures for Yield Improvement. DFT 2008: 7-15
69	EE	Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault: A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. J. Electronic Testing 24(4): 353-364 (2008)
2007
68	EE	A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Slow write driver faults in 65nm SRAM technology: analysis and March test solution. DATE 2007: 528-533
67		Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: A Mixed Approach for Unified Logic Diagnosis. DDECS 2007: 239-242
66	EE	Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: DERRIC: A Tool for Unified Logic Diagnosis. European Test Symposium 2007: 13-20
65	EE	O. Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. European Test Symposium 2007: 77-84
64	EE	A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. European Test Symposium 2007: 97-104
63	EE	A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. VTS 2007: 361-368
62	EE	O. Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. VTS 2007: 47-52
2006
61	EE	Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich: Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SoC 2006: 403-408
60	EE	O. Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: An Overview of Failure Mechanisms in Embedded Flash Memories. VTS 2006: 108-113
59	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electronic Testing 22(1): 89-99 (2006)
2005
58	EE	Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault: Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. PATMOS 2005: 540-549
57	EE	Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault: Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. VLSI-SoC 2005: 267-281
2004
56	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Design of Routing-Constrained Low Power Scan Chains. DATE 2004: 62-67
55	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Design of Routing-Constrained Low Power Scan Chains. DELTA 2004: 287-294
54	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: Power-Driven Routing-Constrained Scan Chain Design. J. Electronic Testing 20(6): 647-660 (2004)
2003
53	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC 2003: 488-493
52	EE	Marie-Lise Flottes, Christian Landrault, A. Petitqueux: A Unified DFT Approach for BIST and External Test. J. Electronic Testing 19(1): 49-60 (2003)
51	EE	Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault: A Ring Architecture Strategy for BIST Test Pattern Generation. J. Electronic Testing 19(3): 223-231 (2003)
50	EE	Christian Landrault: Guest Editorial. J. Electronic Testing 19(4): 367 (2003)
2002
49	EE	Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Test Power: a Big Issue in Large SOC Designs. DELTA 2002: 447-449
48	EE	Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Power Driven Chaining of Flip-Flops in Scan Architectures. ITC 2002: 796-803
47	EE	René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: On Using Efficient Test Sequences for BIST. VTS 2002: 145-152
46	EE	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich: High Defect Coverage with Low-Power Test Sequences in a BIST Environment. IEEE Design & Test of Computers 19(5): 44-52 (2002)
45	EE	Christian Landrault: Guest Editorial. J. Electronic Testing 18(2): 107 (2002)
44	EE	René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Hardware Generation of Random Single Input Change Test Sequences. J. Electronic Testing 18(2): 145-157 (2002)
2001
43	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Asian Test Symposium 2001: 253-258
42	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Gated Clock Scheme for Low Power Scan-Based BIST. IOLTW 2001: 87-89
41		David Bernard, Christian Landrault, Pascal Nouet: Interconnect Capacitance Modelling in a VDSM CMOS Technology. VLSI-SOC 2001: 133-144
40		René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Random Adjacent Sequences: An Efficient Solution for Logic BIST. VLSI-SOC 2001: 413-424
39	EE	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich: A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. VTS 2001: 306-311
38	EE	Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. J. Electronic Testing 17(3-4): 233-241 (2001)
2000
37	EE	Marie-Lise Flottes, Christian Landrault, A. Petitqueux: Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. Asian Test Symposium 2000: 404-
36	EE	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: An adjacency-based test pattern generator for low power BIST design. Asian Test Symposium 2000: 459-464
35	EE	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. IOLTW 2000: 121-126
34		Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch: Low power BIST design by hypergraph partitioning: methodology and architectures. ITC 2000: 652-661
33	EE	Laurent Bréhélin, Olivier Gascuel, Gilles Caraux, Patrick Girard, Christian Landrault: Hidden Markov and Independence Models with Patterns for Sequential BIST. VTS 2000: 359-368
32	EE	Christian Landrault: Guest Editorial. J. Electronic Testing 16(3): 167 (2000)
31	EE	Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, P. Teixeira, M. Santos: Low Power BIST by Filtering Non-Detecting Vectors. J. Electronic Testing 16(3): 193-202 (2000)
1999
30	EE	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. Asian Test Symposium 1999: 89-94
29	EE	A. Toulouse, David Bernard, Christian Landrault, Pascal Nouet: Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts. DATE 1999: 576-580
28	EE	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. Great Lakes Symposium on VLSI 1999: 24-
27	EE	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, P. Teixeira, M. Santos: Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) 1999: 110-113
26	EE	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Test Vector Inhibiting Technique for Low Energy BIST Design. VTS 1999: 407-412
25	EE	Christian Landrault: Guest Editorial. J. Electronic Testing 14(1-2): 11 (1999)
24	EE	Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel: A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. J. Electronic Testing 14(1-2): 95-102 (1999)
1998
23	EE	Christophe Fagot, Olivier Gascuel, Patrick Girard, Christian Landrault: A Ring Architecture Strategy for BIST Test Pattern Generation. Asian Test Symposium 1998: 418-423
22	EE	Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel: A BIST Structure to Test Delay Faults in a Scan Environment. Asian Test Symposium 1998: 435-439
1997
21	EE	Marc Perbost, Ludovic Le Lan, Christian Landrault: Automatic Testability Analysis of Boards and MCMs at Chip Level. Asian Test Symposium 1997: 36-41
20	EE	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac: A gate resizing technique for high reduction in power consumption. ISLPED 1997: 281-286
19		Christophe Fagot, Patrick Girard, Christian Landrault: On Using Machine Learning for Logic BIST. ITC 1997: 338-346
18	EE	J. Abraham, P. Frankl, Christian Landrault, Meryem Marzouki, Paolo Prinetto, Chantal Robach, Pascale Thévenod-Fosse: Hardware Test: Can We Learn from Software Testing? VTS 1997: 320-321
17	EE	Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch: An optimized BIST test pattern generator for delay testing. VTS 1997: 94-100
16	EE	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac: A non-iterative gate resizing algorithm for high reduction in power consumption. Integration 24(1): 37-52 (1997)
1996
15		Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez: A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. ITC 1996: 286-293
14	EE	S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: A new test pattern generation method for delay fault testing. VTS 1996: 296-301
1995
13	EE	S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault: Test configurations to enhance the testability of sequential circuits. Asian Test Symposium 1995: 160-168
12		Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre: Is High-Level Test Synthesis Just Design for Test? ITC 1995: 294
11	EE	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez: Diagnostic of path and gate delay faults in non-scan sequential circuits. VTS 1995: 380-386
10	EE	Patrick Girard, Christian Landrault, Serge Pravossoudovitch: An advanced diagnostic method for delay faults in combinational faulty circuits. J. Electronic Testing 6(3): 277-294 (1995)
1994
9		D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. EDAC-ETC-EUROASIC 1994: 518-523
1993
8		D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. ITC 1993: 705-713
1992
7	EE	Patrick Girard, Christian Landrault, Serge Pravossoudovitch: A Novel Approach to Delay-Fault Diagnosis. DAC 1992: 357-360
6	EE	Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Delay-Fault Diagnosis by Critical-Path Tracing. IEEE Design & Test of Computers 9(4): 27-32 (1992)
1991
5	EE	Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch: Fault modeling and fault equivalence in CMOS technology. J. Electronic Testing 2(3): 229-241 (1991)
1990
4	EE	Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch: Fault modelling and fault equivalence in CMOS technology. EURO-DAC 1990: 407-412
1980
3		Yves Crouzet, Christian Landrault: Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor. IEEE Trans. Computers 29(6): 532-537 (1980)
1978
2		Christian Landrault, Jean-Claude Laprie: SURF - A Program for Modeling and Reliability Prediction for Fault-Tolerant Computing Systems. Jerusalem Conference on Information Technology 1978: 17-26
1		Alain Costes, Christian Landrault, Jean-Claude Laprie: Reliability and Availability Models for Maintained Systems Featuring Hardware Failures and Design Faults. IEEE Trans. Computers 27(6): 548-560 (1978)

Coauthor Index

1	J. Abraham	[18]
2	Nabil Badereddine	[57] [58] [61] [69]
3	Magali Bastian	[63] [64] [68]
4	David Bernard	[29] [41]
5	Yves Bertrand	[13]
6	Yannick Bonhomme	[42] [43] [48] [49] [53] [54] [55] [56] [59]
7	Alberto Bosio	[66] [67] [70] [71]
8	Laurent Bréhélin	[33]
9	Gilles Caraux	[33]
10	Krishnendu Chakrabarty	[69]
11	Marylene Combe	[60]
12	Alain Costes	[1]
13	S. Cremoux	[14]
14	Yves Crouzet	[3]
15	Jean Michel Daga	[60] [62] [65]
16	René David	[38] [40] [44] [47]
17	D. Dumas	[8] [9]
18	Christophe Fagot	[14] [19] [23] [51]
19	Joan Figueras	[27] [31]
20	Marie-Lise Flottes	[4] [5] [12] [37] [52]
21	P. Frankl	[18]
22	A. Gabarró	[31]
23	Olivier Gascuel	[23] [33] [51]
24	O. Ginez	[60] [62] [65]
25	Patrick Girard	[6] [7] [8] [9] [10] [11] [14] [15] [16] [17] [19] [20] [22] [23] [24] [26] [27] [28] [30] [31] [33] [34] [35] [36] [38] [39] [40] [42] [43] [44] [46] [47] [48] [49] [51] [53] [54] [55] [56] [57] [58] [59] [60] [61] [62] [63] [64] [65] [66] [67] [68] [69] [70] [71]
26	Loïs Guiller	[26] [27] [28] [30] [31] [34] [36] [39] [42] [43] [53] [54] [55] [56] [59]
27	Ludovic Le Lan	[21]
28	Jean-Claude Laprie	[1] [2]
29	S. Lavabre	[13]
30	M. Lopez	[31]
31	Salvador Manich	[27] [31]
32	Meryem Marzouki	[18]
33	V. Moreda	[17] [22] [24]
34	A. Ney	[63] [64] [68]
35	Pascal Nouet	[29] [41]
36	Marc Perbost	[21]
37	A. Petitqueux	[37] [52]
38	Serge Pravossoudovitch	[4] [5] [6] [7] [8] [9] [10] [11] [14] [15] [16] [17] [20] [22] [24] [26] [27] [28] [30] [31] [34] [35] [36] [38] [39] [40] [42] [43] [44] [46] [47] [48] [49] [53] [54] [55] [56] [57] [58] [59] [60] [61] [62] [63] [64] [65] [66] [67] [68] [69] [70] [71]
39	Paolo Prinetto	[18]
40	Michel Renovell	[13]
41	Chantal Robach	[18]
42	B. Rodriguez	[11] [15]
43	Alexandre Rousset	[66] [67] [71]
44	Bruno Rouzeyre	[12]
45	M. Santos	[27] [31]
46	D. Severac	[16] [20]
47	P. Teixeira	[27] [31]
48	Pascale Thévenod-Fosse	[18]
49	A. Toulouse	[29]
50	Julien Vial	[70]
51	Arnaud Virazel	[22] [24] [35] [38] [40] [44] [46] [47] [55] [56] [57] [58] [59] [60] [61] [62] [63] [64] [65] [66] [67] [68] [69] [70] [71]
52	Zhanglei Wang	[69]
53	Hans-Joachim Wunderlich	[39] [46] [61]

Colors in the list of coauthors