Rubin A. Parekhji

2008
26	EE	Sudhakar Surendran, Rubin A. Parekhji, R. Govindarajan: A systematic approach to synthesis of verification test-suites for modular SoC designs. SoCC 2008: 91-96
25	EE	Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi, Rubin A. Parekhji: A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips. VTS 2008: 53-58
2007
24	EE	Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji: Methodology for low power test pattern generation using activity threshold control logic. ICCAD 2007: 526-529
23	EE	Sandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin A. Parekhji: Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs. VLSI Design 2007: 339-344
22	EE	Subir K. Roy, Rubin A. Parekhji: Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs. VLSI Design 2007: 364-372
21	EE	Satish Yada, Bharadwaj Amrutur, Rubin A. Parekhji: Modified Stability Checking for On-line Error Detection. VLSI Design 2007: 787-792
2006
20	EE	Rubin A. Parekhji: Session Abstract. VTS 2006: 86-87
2005
19	EE	Sameer Goel, Rubin A. Parekhji: Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency. Asian Test Symposium 2005: 330-336
18	EE	Rubin A. Parekhji: DFT for Low Cost SOC Test. Asian Test Symposium 2005: 451
2004
17	EE	Ambar A. Gadkari, S. Ramesh, Rubin A. Parekhji: CESC: a visual formalism for specification and verification of SoCs. ACM Great Lakes Symposium on VLSI 2004: 354-357
16	EE	K. Nikila, Rubin A. Parekhji: DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device. ITC 2004: 773-782
15	EE	Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar: Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories. VLSI Design 2004: 753-756
14		Carol Stolicny, Tapio Koivukangas, Rubin A. Parekhji, Ian G. Harris, Rob Aitken: ITC 2003 panels: Part 1. IEEE Design & Test of Computers 21(2): 160-163 (2004)
2003
13	EE	Rubin A. Parekhji: Panel Synopsis - How (In)Adequate is One Time Testing?. ITC 2003: 1279
12	EE	Rubin A. Parekhji: Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions. VLSI Design 2003: 17
2002
11	EE	Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji: Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. VLSI Design 2002: 781-788
2000
10	EE	Ameet Bagwe, Rubin A. Parekhji: Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems. Asian Test Symposium 2000: 260-
9		Jais Abraham, Narayan Prasad, Srinivasa Chakravarthy B. S., Ameet Bagwe, Rubin A. Parekhji: A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx. ITC 2000: 417-425
8		Rubin A. Parekhji: Test Techniques and Trade-offs for Embedded Cores and Systems. VLSI Design 2000: 5
1996
7	EE	Michael Nicolaidis, Rubin A. Parekhji, M. Boudjit: E-Groups: A New Technique for Fast Backward Propagation in System Level Test Generation. Asian Test Symposium 1996: 34-41
6	EE	Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar: Monitoring machine based synthesis technique for concurrent error detection in finite state machines. J. Electronic Testing 8(2): 179-201 (1996)
1995
5	EE	B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh: A new methodology for the design of low-cost fail safe circuits and networks. VLSI Design 1995: 355-358
4	EE	Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar: Concurrent Error Detection Using Monitoring Machines. IEEE Design & Test of Computers 12(3): 24-32 (1995)
1993
3		Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar: State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. VLSI Design 1993: 15-20
1991
2		Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar: A Methodology for Designing Optimal Self-Checking Sequential Circuits. ITC 1991: 283-291
1989
1	EE	Rubin A. Parekhji, N. K. Nanda: Design methodology and microdiagnostics development for a self-checking microprocessor. MICRO 1989: 70-82

Coauthor Index

1	Jais Abraham	[9] [11] [23]
2	Rob Aitken	[14]
3	Bharadwaj Amrutur	[21]
4	Ameet Bagwe	[9] [10]
5	M. Boudjit	[7]
6	Arun N. Chandorkar	[15]
7	V. R. Devanathan	[24]
8	Amit Dutta	[23]
9	Ambar A. Gadkari	[17]
10	Sameer Goel	[19]
11	R. Govindarajan	[26]
12	Ian G. Harris	[14]
13	Shyam S. Jagini	[11]
14	Sandeep Jain	[23]
15	Sumant Kale	[23]
16	B. Ravi Kishore	[5]
17	Tapio Koivukangas	[14]
18	Parag Mhatre	[11]
19	N. K. Nanda	[1]
20	Michael Nicolaidis	[7]
21	K. Nikila	[16]
22	Sandeep Pagey	[5]
23	Narayan Prasad	[9]
24	S. Ramesh (Sethu Ramesh)	[17]
25	Jagdish C. Rao	[11]
26	Srivaths Ravi	[24] [25]
27	Subir K. Roy	[22]
28	Srinivasa Chakravarthy B. S.	[9]
29	Rajeshwar S. Sable	[15]
30	M. Sambandam	[11]
31	Ravindra P. Saraf	[15]
32	Soujanna Sarkar	[11]
33	Karanth Shankaranarayana	[11]
34	Sunil D. Sherlekar	[2] [3] [4] [5] [6]
35	K. P. Sheshadri	[11]
36	Abhijeet Shrivastava	[25]
37	Carol Stolicny	[14]
38	Sudhakar Surendran	[26]
39	S. Talapatra	[11]
40	Rajesh Tiwari	[25]
41	H. Udayakumar	[11]
42	G. Venkatesh	[2] [3] [4] [5] [6]
43	N. Venkatesh	[11]
44	R. Venkatraman	[11]
45	Srinivas Kumar Vooka	[23]
46	Mahit Warhadpande	[25]
47	Satish Yada	[21]

Colors in the list of coauthors