ITC 2002:
Baltimore,
MD,
USA
Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002.
IEEE Computer Society 2002 BibTeX
Homegrown versus Commercial Solutions for Low-Cost Text
Testing the Tester
Plenary
Memory Testing
Advances in Soc Testing
- Bart Vermeulen, Tom Waayers, Sjaak Bakker:
EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips.
55-63
Electronic Edition (link) BibTeX
- Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici:
Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing.
64-73
Electronic Edition (link) BibTeX
- Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan:
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm.
74-82
Electronic Edition (link) BibTeX
Defect-Oriented Test
High-Performance Timing Measurements
Test Data Reduction
Memory DFT,
Bist and Repair
- O. Hirabayashi, A. Suzuki, T. Yabe, A. Kawasumi, Y. Takeyama, K. Kushida, A. Tohata, N. Otsuka:
DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs.
164-169
Electronic Edition (link) BibTeX
- Shigeki Tomishima, Hiroaki Tanizaki, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka, T. Tada, Kenji Gamo:
A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test.
170-177
Electronic Edition (link) BibTeX
- Bruce Cowan, Owen Farnsworth, Peter Jakobsen, Steven F. Oakland, Michael Ouellette, Donald L. Wheater:
On-Chip Repair and an ATE Independent Fusing Methodology.
178-186
Electronic Edition (link) BibTeX
- Jayasanker Jayabalan, Juraj Povazanec:
Integration of SRAM Redundancy into Production Test.
187-193
Electronic Edition (link) BibTeX
Design Validation - Novel ATPG Applications
- Jacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab:
Verifying Properties Using Sequential ATPG.
194-202
Electronic Edition (link) BibTeX
- Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir:
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems.
203-212
Electronic Edition (link) BibTeX
- Jayanta Bhadra, Narayanan Krishnamurthy:
Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits.
213-222
Electronic Edition (link) BibTeX
- Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri:
Design Rewiring Using ATPG.
223-232
Electronic Edition (link) BibTeX
Novel Techniques for Diagnostics
- Ronald D. Blanton, John T. Chen, Rao Desineni, Kumar N. Dwarakanath, Wojciech Maly, Thomas J. Vogels:
Fault Tuples in Diagnosis of Deep-Submicron Circuits.
233-241
Electronic Edition (link) BibTeX
- Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura:
A Persistent Diagnostic Technique for Unstable Defects.
242-249
Electronic Edition (link) BibTeX
- David B. Lavo, Ismed Hartanto, Tracy Larrabee:
Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis.
250-259
Electronic Edition (link) BibTeX
- Camelia Hora, Rene Segers, Stefan Eichenberger, Maurice Lousberg:
An Effective Diagnosis Method to Support Yield Improvement.
260-269
Electronic Edition (link) BibTeX
Connecting Disconnects
Test Data Compression
- Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian:
Embedded Deterministic Test for Low-Cost Manufacturing Test.
301-310
Electronic Edition (link) BibTeX
- Subhasish Mitra, Kee Sup Kim:
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction.
311-320
Electronic Edition (link) BibTeX
- C. V. Krishna, Nur A. Touba:
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression.
321-330
Electronic Edition (link) BibTeX
- Francis G. Wolff, Christos A. Papachristou:
Multiscan-Based Test Compression and Hardware Decompression Using LZ77.
331-339
Electronic Edition (link) BibTeX
Lecture Series - Embedded IP for Soc Infrastructure
Chip-Level Crosstalk Identification and Testing
Advances in Fault Simulation and Test Generation
- A. V. S. S. Prasad, Vishwani D. Agrawal, Madhusudan V. Atre:
A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets.
391-397
Electronic Edition (link) BibTeX
- Li-C. Wang, Magdy S. Abadir, Juhong Zhu:
On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults.
398-406
Electronic Edition (link) BibTeX
- Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams:
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme.
407-416
Electronic Edition (link) BibTeX
Adventures in Interfacing
DFT Testers
Production Test Automation
Soft and Hard Failure Analysis and On-Line Testing
Soc Benchmarks
Appliaction Series - High-Speed Test Interfaces
Test and Debug of Microprocessors
- B. Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina:
Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture.
574-583
Electronic Edition (link) BibTeX
- Timothe Litt:
Support for Debugging in the Alpha 21364 Microprocessor.
584-589
Electronic Edition (link) BibTeX
- Praveen Parvathala, Kaila Maneparambil, William Lindsay:
FRITS - A Microprocessor Functional BIST Method.
590-598
Electronic Edition (link) BibTeX
FPGA Testing
Lecture Series-Silicon Debug
- Hari Balachandran, Kenneth M. Butler, Neil Simpson:
Facilitating Rapid First Silicon Debug.
628-637
Electronic Edition (link) BibTeX
- Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel:
Core-Based Scan Architecture for Silicon Debug.
638-647
Electronic Edition (link) BibTeX
- Xinli Gu, Weili Wang, Kevin Li, Heon C. Kim, Sung Soo Chung:
Re-Using DFT Logic for Functional and Silicon Debugging Test.
648-656
Electronic Edition (link) BibTeX
- Don Douglas Josephson:
The Manic Depression of Microprocessor Debug.
657-663
Electronic Edition (link) BibTeX
- Carol Pyron, Rekha Bangalore, Dawit Belete, Jason Goertz, Ashutosh Razdan, Denise Younger:
Silicon Symptoms to Solutions: Applying Design for Debug Techniques.
664-672
Electronic Edition (link) BibTeX
Data Analysis and Yield Model Validation
- Robert Madge, B. H. Goh, V. Rajagopalan, C. Macchietto, W. Robert Daasch, Chris Schuermyer, C. Taylor, David Turner:
Screening MinVDD Outliers Using Feed-Forward Voltage Testing.
673-682
Electronic Edition (link) BibTeX
- Minh Quach, Tuan Pham, Tim Figal, Bob Kopitzke, Pete O'Neill:
Wafer-Level Defect-Based Testing Using Enhanced Voltage Stress and Statistical Test Data Evaluation.
683-692
Electronic Edition (link) BibTeX
- Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh:
Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model.
693-699
Electronic Edition (link) BibTeX
Jitter Testing in Multi-Gigahertz Digital Systems
Efficient Approaches to Soc Testing
1149.1 Verification and Validation
Scan Stitching
- David Berthelot, Samit Chaudhuri, Hamid Savoj:
An Efficient Linear Time Algorithm for Scan Chain Optimization and Repartitioning.
781-787
Electronic Edition (link) BibTeX
- Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur:
Integrating DFT in the Physical Synthesis Flow.
788-795
Electronic Edition (link) BibTeX
- Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Power Driven Chaining of Flip-Flops in Scan Architectures.
796-803
Electronic Edition (link) BibTeX
- Frank te Beest, Ad M. G. Peeters, Marc Verra, Kees van Berkel, Hans G. Kerkhoff:
Automatic Scan Insertion and Test Generation for Asynchronous Circuits.
804-813
Electronic Edition (link) BibTeX
DFT for Manufacturing Problems
Mixed-Signal Test Techniques
Go-Fast ATE!
System Test Design,
Bist and System Verification
Advances in IDDX
Delay-Test
Embedded Test for Analog and Digital
Maximizing Test Effectiveness and Minimizing Cost
Board Test and Bist for Mems
Debug and Diagnosis
Delay-Test:
Practical Experience and Solutions
- Dawit Belete, Ashutosh Razdan, William Schwarz, Rajesh Raina, Christopher Hawkins, Jeff Morehead:
Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor .
1111-1119
Electronic Edition (link) BibTeX
- Jayashree Saxena, Kenneth M. Butler, John Gatt, R. Raghuraman, Sudheendra Phani Kumar, Supatra Basu, David J. Campbell, John Berech:
Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges .
1120-1129
Electronic Edition (link) BibTeX
- Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi:
A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits.
1130-1139
Electronic Edition (link) BibTeX
RF Testing
Test Resource
Can System Test and IC Test Learn from Each Other?
Taps All Over My Chips
Can Scan Achieve The Quality Level We Are Looking For?
Mixed-Signal Bist:
Fact or Fiction?
Mission Possible?:
An Open Ate Tester Architecture
The Impacts of Outsourcing on Test
Test and Repair of Commodity and Embedded Flash Memories
Testing Highly Integrated Circuits and Systems Using A Low-Cost Tester:
How to Overcome The Challenge?
Multi-GHZ Era:
Test Challenges and Solutions
Board Test and ITC:
What Does the Future Hold?
2001 ITC Best Paper
Copyright © Sat May 16 23:26:44 2009
by Michael Ley (ley@uni-trier.de)
