| 2005 |
|---|
| 9 | EE | Bhaskar Chatterjee,
Manoj Sachdev:
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology.
IEEE Trans. VLSI Syst. 13(11): 1296-1304 (2005) |
| 8 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ram Krishnamurthy:
Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies.
Microelectronics Journal 36(9): 801-809 (2005) |
| 2004 |
|---|
| 7 | | Christine Kwong,
Bhaskar Chatterjee,
Manoj Sachdev:
Modeling and designing energy-delay optimized wide domino circuits.
ISCAS (2) 2004: 921-924 |
| 6 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ram Krishnamurthy:
A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies.
ISLPED 2004: 248-251 |
| 5 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ram Krishnamurthy:
Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies.
ISQED 2004: 415-420 |
| 4 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ali Keshavarzi:
A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs.
ITC 2004: 1108-1117 |
| 3 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ali Keshavarzi:
DFT for Delay Fault Testing of High-Performance Digital Circuits.
IEEE Design & Test of Computers 21(3): 248-258 (2004) |
| 2003 |
|---|
| 2 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Steven Hsu,
Ram Krishnamurthy,
Shekhar Borkar:
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies.
ISLPED 2003: 122-127 |
| 2002 |
|---|
| 1 | EE | Bhaskar Chatterjee,
Manoj Sachdev,
Ali Keshavarzi:
A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits.
ITC 2002: 1130-1139 |
