2003 |
14 | EE | Yu Huang,
Wu-Tung Cheng,
Chien-Chung Tsai,
Nilanjan Mukherjee,
Sudhakar M. Reddy:
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets.
ISQED 2003: 99-104 |
2002 |
13 | EE | Yu Huang,
Sudhakar M. Reddy,
Wu-Tung Cheng,
Paul Reuter,
Nilanjan Mukherjee,
Chien-Chung Tsai,
Omer Samman,
Yahya Zaidan:
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm.
ITC 2002: 74-82 |
12 | EE | Yu Huang,
Nilanjan Mukherjee,
Chien-Chung Tsai,
Omer Samman,
Yahya Zaidan,
Yanping Zhang,
Wu-Tung Cheng,
Sudhakar M. Reddy:
Constraint Driven Pin Mapping for Concurrent SOC Testing.
VLSI Design 2002: 511-516 |
11 | EE | Yu Huang,
Chien-Chung Tsai,
Nilanjan Mukherjee,
Omer Samman,
Wu-Tung Cheng,
Sudhakar M. Reddy:
Synthesis of Scan Chains for Netlist Descriptions at RT-Level.
J. Electronic Testing 18(2): 189-201 (2002) |
10 | EE | Yu Huang,
Wu-Tung Cheng,
Chien-Chung Tsai,
Nilanjan Mukherjee,
Omer Samman,
Yahya Zaidan,
Sudhakar M. Reddy:
On Concurrent Test of Core-Based SOC Design.
J. Electronic Testing 18(4-5): 401-414 (2002) |
2001 |
9 | EE | Yu Huang,
Wu-Tung Cheng,
Chien-Chung Tsai,
Nilanjan Mukherjee,
Omer Samman,
Yahya Zaidan,
Sudhakar M. Reddy:
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D.
Asian Test Symposium 2001: 265- |
8 | | Yu Huang,
Chien-Chung Tsai,
Neelanjan Mukherjee,
Omer Samman,
Dan Devries,
Wu-Tung Cheng,
Sudhakar M. Reddy:
On RTL scan design.
ITC 2001: 728-737 |
1998 |
7 | EE | Shih-Chieh Chang,
Shi-Sen Chang,
Wen-Ben Jone,
Chien-Chung Tsai:
A novel combinational testability analysis by considering signal correlation.
ITC 1998: 658-667 |
1997 |
6 | | Chien-Chung Tsai,
Malgorzata Marek-Sadowska:
Boolean Functions Classification via Fixed Polarity Reed-Muller Forms.
IEEE Trans. Computers 46(2): 173-186 (1997) |
1996 |
5 | EE | Chien-Chung Tsai,
Malgorzata Marek-Sadowska:
Multilevel Logic Synthesis for Arithmetic Functions.
DAC 1996: 242-247 |
4 | EE | Chien-Chung Tsai,
Malgorzata Marek-Sadowska:
Logic Synthesis for Testability.
Great Lakes Symposium on VLSI 1996: 118-121 |
3 | | Chien-Chung Tsai,
Malgorzata Marek-Sadowska:
Generalized Reed-Muller Forms as a Tool to Detect Symmetries.
IEEE Trans. Computers 45(1): 33-40 (1996) |
1994 |
2 | EE | Chien-Chung Tsai,
Malgorzata Marek-Sadowska:
Boolean Matching Using Generalized Reed-Muller Forms.
DAC 1994: 339-344 |
1 | | Chien-Chung Tsai,
Malgorzata Marek-Sadowska:
Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms.
ISCAS 1994: 287-290 |