| 2002 |
|---|
| 11 | EE | Terry Tao Ye,
Samit Chaudhuri,
F. Huang,
Hamid Savoj,
Giovanni De Micheli:
Physical synthesis for ASIC datapath circuits.
ISCAS (3) 2002: 365-368 |
| 10 | EE | David Berthelot,
Samit Chaudhuri,
Hamid Savoj:
An Efficient Linear Time Algorithm for Scan Chain Optimization and Repartitioning.
ITC 2002: 781-787 |
| 1999 |
|---|
| 9 | EE | Samit Chaudhuri,
Robert A. Walker:
Bounding Algorithms for Design Space Exploration.
Great Lakes Symposium on VLSI 1999: 234-235 |
| 1997 |
|---|
| 8 | EE | Samit Chaudhuri,
S. A. Blthye,
Robert A. Walker:
A solution methodology for exact design space exploration in a three-dimensional design space.
IEEE Trans. VLSI Syst. 5(1): 69-81 (1997) |
| 1996 |
|---|
| 7 | EE | Samit Chaudhuri,
Michael Quayle:
Synthesis using sequential functional modules (SFMs).
ICCAD 1996: 436-441 |
| 6 | EE | Samit Chaudhuri,
Robert A. Walker:
Computing lower bounds on functional units before scheduling.
IEEE Trans. VLSI Syst. 4(2): 273-279 (1996) |
| 1995 |
|---|
| 5 | EE | Samit Chaudhuri,
Stephen A. Blythe,
Robert A. Walker:
An exact methodology for scheduling in a 3D design space.
ISSS 1995: 78-83 |
| 4 | EE | Robert A. Walker,
Samit Chaudhuri:
Introduction to the Scheduling Problem.
IEEE Design & Test of Computers 12(2): 60-69 (1995) |
| 1994 |
|---|
| 3 | | Samit Chaudhuri,
Robert A. Walker:
ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis.
VLSI Design 1994: 17-20 |
| 2 | EE | Samit Chaudhuri,
Robert A. Walker,
J. E. Mitchell:
Analyzing and exploiting the structure of the constraints in the ILP approach to the scheduling problem.
IEEE Trans. VLSI Syst. 2(4): 456-471 (1994) |
| 1993 |
|---|
| 1 | | Samit Chaudhuri,
Robert A. Walker,
John Mitchell:
The Structure of Assignment, Precedence, and Resource Constraints in the ILP Approach to the Scheduling Problem.
ICCD 1993: 25-29 |
