| 2005 |
|---|
| 13 | EE | Ganapathy Parthasarathy,
Madhu K. Iyer,
Kwang-Ting Cheng,
Forrest Brewer:
Structural search for RTL with predicate learning.
DAC 2005: 451-456 |
| 12 | EE | Feng Lu,
Madhu K. Iyer,
Ganapathy Parthasarathy,
Li-C. Wang,
Kwang-Ting Cheng,
Kuang-Chien Chen:
An Efficient Sequential SAT Solver With Improved Search Strategies.
DATE 2005: 1102-1107 |
| 11 | EE | Madhu K. Iyer,
Ganapathy Parthasarathy,
Kwang-Ting Cheng:
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver.
DATE 2005: 666-671 |
| 10 | | Ganapathy Parthasarathy,
Madhu K. Iyer,
Kwang-Ting Cheng,
Forrest Brewer:
RTL SAT simplification by Boolean and interval arithmetic reasoning.
ICCAD 2005: 297-302 |
| 2004 |
|---|
| 9 | EE | Ganapathy Parthasarathy,
Madhu K. Iyer,
Kwang-Ting Cheng,
Li-C. Wang:
Efficient reachability checking using sequential SAT.
ASP-DAC 2004: 418-423 |
| 8 | EE | Ganapathy Parthasarathy,
Madhu K. Iyer,
Kwang-Ting Cheng,
Li-C. Wang:
An efficient finite-domain constraint solver for circuits.
DAC 2004: 212-217 |
| 7 | EE | Ganapathy Parthasarathy,
Madhu K. Iyer,
Kwang-Ting Cheng,
Li-C. Wang:
Safety Property Verification Using Sequential SAT and Bounded Model Checking.
IEEE Design & Test of Computers 21(2): 132-143 (2004) |
| 2003 |
|---|
| 6 | EE | Madhu K. Iyer,
Ganapathy Parthasarathy,
Kwang-Ting Cheng:
SATORI - A Fast Sequential SAT Engine for Circuits.
ICCAD 2003: 320-325 |
| 2002 |
|---|
| 5 | EE | Ganapathy Parthasarathy,
Madhu K. Iyer,
Tao Feng,
Li-C. Wang,
Kwang-Ting Cheng,
Magdy S. Abadir:
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems.
ITC 2002: 203-212 |
| 4 | EE | Madhu K. Iyer,
Kwang-Ting Cheng:
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs.
VTS 2002: 139-144 |
| 2001 |
|---|
| 3 | EE | Jing-Reng Huang,
Madhu K. Iyer,
Kwang-Ting Cheng:
A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs.
VTS 2001: 198-203 |
| 1999 |
|---|
| 2 | EE | Madhu K. Iyer,
Michael L. Bushnell:
Effect of Noise on Analog Circuit Testing.
J. Electronic Testing 15(1-2): 11-22 (1999) |
| 1998 |
|---|
| 1 | EE | Madhu K. Iyer,
Michael L. Bushnell:
Effect of Noise on Analog Circuit Testing.
VTS 1998: 138-144 |
