| 2002 |
|---|
| 6 | EE | Kazumi Hatayama,
Michinobu Nakao,
Yasuo Sato:
At-Speed Built-in Test for Logic Circuits with Multiple Clocks.
Asian Test Symposium 2002: 292-297 |
| 5 | EE | Kazumi Hatayama,
Michinobu Nakao,
Yoshikazu Kiyoshige,
Koichiro Natsume,
Yasuo Sato,
Takaharu Nagumo:
Application of High-Quality Built-In Test to Industrial Designs.
ITC 2002: 1003-1012 |
| 2001 |
|---|
| 4 | EE | Michinobu Nakao,
Yoshikazu Kiyoshige,
Kazumi Hatayama,
Yasuo Sato,
Takaharu Nagumo:
Test Generation for Multiple-Threshold Gate-Delay Fault Model.
Asian Test Symposium 2001: 244- |
| 1999 |
|---|
| 3 | | Michinobu Nakao,
Seiji Kobayashi,
Kazumi Hatayama,
Kazuhiko Iijima,
Seiji Terada:
Low overhead test point insertion for scan-based BIST.
ITC 1999: 348-357 |
| 1997 |
|---|
| 2 | EE | Michinobu Nakao,
Kazumi Hatayama,
Isao Higashi:
Accelerated Test Points Selection Method for Scan-Based BIST.
Asian Test Symposium 1997: 359- |
| 1995 |
|---|
| 1 | EE | Hiroshi Date,
Michinobu Nakao,
Kazumi Hatayama:
A parallel sequential test generation system DESCARTES based on real-valued logic simulation.
Asian Test Symposium 1995: 252-258 |
