| 2005 |
|---|
| 14 | EE | Ganapathy Parthasarathy,
Madhu K. Iyer,
Kwang-Ting Cheng,
Forrest Brewer:
Structural search for RTL with predicate learning.
DAC 2005: 451-456 |
| 13 | EE | Feng Lu,
Madhu K. Iyer,
Ganapathy Parthasarathy,
Li-C. Wang,
Kwang-Ting Cheng,
Kuang-Chien Chen:
An Efficient Sequential SAT Solver With Improved Search Strategies.
DATE 2005: 1102-1107 |
| 12 | EE | Madhu K. Iyer,
Ganapathy Parthasarathy,
Kwang-Ting Cheng:
Efficient Conflict-Based Learning in an RTL Circuit Constraint Solver.
DATE 2005: 666-671 |
| 11 | | Ganapathy Parthasarathy,
Madhu K. Iyer,
Kwang-Ting Cheng,
Forrest Brewer:
RTL SAT simplification by Boolean and interval arithmetic reasoning.
ICCAD 2005: 297-302 |
| 2004 |
|---|
| 10 | EE | Ganapathy Parthasarathy,
Madhu K. Iyer,
Kwang-Ting Cheng,
Li-C. Wang:
Efficient reachability checking using sequential SAT.
ASP-DAC 2004: 418-423 |
| 9 | EE | Ganapathy Parthasarathy,
Madhu K. Iyer,
Kwang-Ting Cheng,
Li-C. Wang:
An efficient finite-domain constraint solver for circuits.
DAC 2004: 212-217 |
| 8 | EE | Ganapathy Parthasarathy,
Madhu K. Iyer,
Kwang-Ting Cheng,
Li-C. Wang:
Safety Property Verification Using Sequential SAT and Bounded Model Checking.
IEEE Design & Test of Computers 21(2): 132-143 (2004) |
| 2003 |
|---|
| 7 | EE | Madhu K. Iyer,
Ganapathy Parthasarathy,
Kwang-Ting Cheng:
SATORI - A Fast Sequential SAT Engine for Circuits.
ICCAD 2003: 320-325 |
| 2002 |
|---|
| 6 | EE | Ganapathy Parthasarathy,
Madhu K. Iyer,
Tao Feng,
Li-C. Wang,
Kwang-Ting Cheng,
Magdy S. Abadir:
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems.
ITC 2002: 203-212 |
| 5 | EE | Amit Singh,
Ganapathy Parthasarathy,
Malgorzata Marek-Sadowska:
Efficient circuit clustering for area and power reduction in FPGAs.
ACM Trans. Design Autom. Electr. Syst. 7(4): 643-663 (2002) |
| 2001 |
|---|
| 4 | EE | Amit Singh,
Ganapathy Parthasarathy,
Malgorzata Marek-Sadowska:
Interconnect Resource-Aware Placement for Hierarchical FPGAs.
ICCAD 2001: 132-136 |
| 3 | EE | Ganapathy Parthasarathy,
Malgorzata Marek-Sadowska,
Arindam Mukherjee,
Amit Singh:
Interconnect complexity-aware FPGA placement using Rent's rule.
SLIP 2001: 115-121 |
| 1999 |
|---|
| 2 | EE | Vishwani D. Agrawal,
Michael L. Bushnell,
Ganapathy Parthasarathy,
Rajesh Ramadoss:
Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method.
VLSI Design 1999: 434-439 |
| 1998 |
|---|
| 1 | EE | Ganapathy Parthasarathy,
Michael L. Bushnell:
Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion.
VTS 1998: 210-217 |
