2008 | ||
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38 | EE | Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits. DDECS 2008: 34-37 |
2007 | ||
37 | Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits. DDECS 2007: 295-300 | |
36 | EE | Jorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino Bicho Dos Santos, Isabel C. Teixeira, João Paulo Teixeira: Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations. DFT 2007: 303-311 |
35 | EE | Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits. IOLTS 2007: 167-172 |
34 | EE | Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Enhancing the Tolerance to Power-Supply Instability in Digital Circuits. ISVLSI 2007: 207-212 |
2006 | ||
33 | F. Guerreiro, Jorge Semião, A. Pierce, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage. DDECS 2006: 279-284 | |
32 | EE | M. Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira: Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes. IOLTS 2006: 257-262 |
2005 | ||
31 | C. Leong, P. Bento, P. Rodrigues, A. Trindade, J. C. Silva, P. Lousã, J. Rego, J. Nobre, J. Varela, João Paulo Teixeira, Isabel C. Teixeira: Design and Test Methodology for a Reconfigurable PEM Data Acquisition Electronics System. FPL 2005: 523-526 | |
30 | EE | M. Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test. IOLTS 2005: 281-286 |
29 | EE | D. Barros Júnior, M. Rodríguez-Irago, Marcelino B. Santos, Isabel C. Teixeira, Fabian Vargas, João Paulo Teixeira: Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip. J. Electronic Testing 21(4): 349-363 (2005) |
2004 | ||
28 | EE | Daniel Barros Jr., Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Modeling and Simulation of Time Domain Faults in Digital Systems. IOLTS 2004: 5-10 |
27 | EE | Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, L. Balado, Joan Figueras: On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level. J. Electronic Testing 20(4): 345-355 (2004) |
2003 | ||
26 | EE | Marcelino B. Santos, José M. Fernandes, Isabel C. Teixeira, João Paulo Teixeira: RTL Test Pattern Generation for High Quality Loosely Deterministic BIST. DATE 2003: 10994-10999 |
25 | EE | Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems. IOLTS 2003: 164-165 |
2002 | ||
24 | EE | Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling. DFT 2002: 216-224 |
23 | EE | Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras: RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. ITC 2002: 814-823 |
22 | EE | Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira: RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage. J. Electronic Testing 18(2): 179-187 (2002) |
21 | EE | Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System. J. Electronic Testing 18(3): 285-294 (2002) |
2001 | ||
20 | EE | Yervant Zorian, Paolo Prinetto, João Paulo Teixeira, Isabel C. Teixeira, Carlos Eduardo Pereira, Octávio Páscoa Dias, Jorge Semião, Peter Muhmenthaler, W. Radermacher: Embedded tutorial: TRP: integrating embedded test and ATE. DATE 2001: 34-37 |
19 | Hugo Lérias, João Luz, Pedro Moura, Ana Mendes, Isabel C. Teixeira, João Paulo Teixeira: Towards E-Management as Enabler for Accelerated Change. ICEIS (2) 2001: 807-814 | |
18 | EE | Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro. IOLTW 2001: 197-201 |
17 | Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level. ITC 2001: 377-385 | |
16 | EE | Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira: RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems. J. Electronic Testing 17(3-4): 311-319 (2001) |
2000 | ||
15 | Octávio Páscoa Dias, Isabel C. Teixeira, João Paulo Teixeira, Leandro Buss Becker, Carlos Eduardo Pereira: Optimizing Functional distribution in Complex System Design. DIPES 2000: 75-86 | |
14 | EE | Leandro Buss Becker, Carlos Eduardo Pereira, Octávio Páscoa Dias, Isabel C. Teixeira, João Paulo Teixeira: MOSYS A Methodology for Automatic Object Identification from System Specification. ISORC 2000: 198-201 |
13 | EE | Octávio Páscoa Dias, Jorge Semião, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Quality of Electronic Design: From Architectural Level to Test Coverage. ISQED 2000: 197- |
1999 | ||
12 | EE | Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira: Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique. VTS 1999: 326-332 |
11 | EE | Octávio Páscoa Dias, Isabel C. Teixeira, João Paulo Teixeira: Metrics and Criteria for Quality Assessment of Testable Hw/Sw Systems Architectures. J. Electronic Testing 14(1-2): 149-158 (1999) |
1998 | ||
10 | Octávio Páscoa Dias, Isabel C. Teixeira, João Paulo Teixeira, Carlos Eduardo Pereira: An OO Based Methodology for Real-Time HW/SW Systems Modeling. DIPES 1998: 213-222 | |
9 | EE | Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Defect-oriented test quality assessment using fault sampling and simulation. ITC 1998: 35-42 |
1997 | ||
8 | EE | Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira: Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems. DFT 1997: 29-37 |
1995 | ||
7 | EE | Marcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira: Test preparation for high coverage of physical defects in CMOS digital ICs. VTS 1995: 330-337 |
1994 | ||
6 | M. Calha, Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira: Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs. ITC 1994: 720-728 | |
1993 | ||
5 | Antonio Casimiro, M. Simões, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs. DFT 1993: 109-116 | |
4 | P. Nicolau, J. Barbosa, M. Saraiva, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Realistic Fault Analysis of CMOS Analog Building Blocks. DFT 1993: 311-318 | |
1992 | ||
3 | M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira: Physical DFT for High Coverage of Realistic Faults. ITC 1992: 642-651 | |
1991 | ||
2 | EE | João Paulo Teixeira, Isabel C. Teixeira, C. F. Beltrá Almeida, Fernando M. Gonçalves, J. Gonçalves: A methodology for testability enhancement at layout level. J. Electronic Testing 1(4): 287-299 (1991) |
1990 | ||
1 | EE | João Paulo Teixeira, Isabel C. Teixeira, C. F. Beltrá Almeida, Fernando M. Gonçalves, J. Gonçalves, R. Crespo: A strategy for testability enhancement at layout level. EURO-DAC 1990: 413-417 |