2008 | ||
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74 | EE | Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen: Diagnosis of Realistic Defects Based on the X-Fault Model. DDECS 2008: 263-266 |
73 | EE | Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara: Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. ICCAD 2008: 52-58 |
72 | EE | Seiji Kajihara, Michiko Inoue: Special Section on Test and Verification of VLSIs. IEICE Transactions 91-D(3): 640-641 (2008) |
71 | EE | Yuta Yamato, Yusuke Nakamura, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara: A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits. IEICE Transactions 91-D(3): 667-674 (2008) |
70 | EE | Kohei Miyase, Kenta Terashima, Xiaoqing Wen, Seiji Kajihara, Sudhakar M. Reddy: On Detection of Bridge Defects with Stuck-at Tests. IEICE Transactions 91-D(3): 683-689 (2008) |
69 | EE | Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita: Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. J. Electronic Testing 24(4): 379-391 (2008) |
2007 | ||
68 | EE | Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja: Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing. DAC 2007: 527-532 |
67 | EE | Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo: Estimation of delay test quality and its application to test generation. ICCAD 2007: 413-417 |
66 | EE | Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita: A Novel ATPG Method for Capture Power Reduction during Scan Testing. IEICE Transactions 90-D(9): 1398-1405 (2007) |
2006 | ||
65 | EE | Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato: A dynamic test compaction procedure for high-quality path delay testing. ASP-DAC 2006: 348-353 |
64 | EE | Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja: Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. ICCD 2006 |
63 | EE | Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita: A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. VTS 2006: 58-65 |
62 | EE | Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara: A Statistical Quality Model for Delay Testing. IEICE Transactions 89-C(3): 349-355 (2006) |
61 | EE | Yoshinobu Higami, Seiji Kajihara, Irith Pomeranz, Shin-ya Kobayashi, Yuzo Takamatsu: On Finding Don't Cares in Test Sequences for Sequential Circuits. IEICE Transactions 89-D(11): 2748-2755 (2006) |
60 | EE | Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita: A Per-Test Fault Diagnosis Method Based on the X-Fault Model. IEICE Transactions 89-D(11): 2756-2765 (2006) |
59 | EE | Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita: A New Method for Low-Capture-Power Test Generation for Scan Testing. IEICE Transactions 89-D(5): 1679-1686 (2006) |
2005 | ||
58 | EE | Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara: Evaluation of the statistical delay quality model. ASP-DAC 2005: 305-310 |
57 | EE | Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty: Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation. ASP-DAC 2005: 59-64 |
56 | EE | Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy: On Improving Defect Coverage of Stuck-at Fault Tests. Asian Test Symposium 2005: 216-223 |
55 | EE | Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato: Path delay test compaction with process variation tolerance. DAC 2005: 845-850 |
54 | EE | Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan: Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores. VLSI Design 2005: 53-58 |
53 | EE | Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita: On Low-Capture-Power Test Generation for Scan Testing. VTS 2005: 265-270 |
52 | EE | Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita: On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies. IEICE Transactions 88-D(4): 703-710 (2005) |
51 | EE | Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka: On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis. IEICE Transactions 88-D(7): 1671-1677 (2005) |
50 | EE | Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja: Efficient Test Set Modification for Capture Power Reduction. J. Low Power Electronics 1(3): 319-330 (2005) |
49 | EE | Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu: Test cost reduction for logic circuits: Reduction of test data volume and test application time. Systems and Computers in Japan 36(6): 69-83 (2005) |
2004 | ||
48 | EE | Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu: Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction. Asian Test Symposium 2004: 46-49 |
47 | EE | Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy: Multiple Scan Tree Design with Test Vector Modification. Asian Test Symposium 2004: 76-81 |
46 | EE | Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita: On per-test fault diagnosis using the X-fault model. ICCAD 2004: 633-640 |
45 | EE | Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara: Random Access Scan: A solution to test power, test data volume and test time. VLSI Design 2004: 883-888 |
44 | EE | Kohei Miyase, Seiji Kajihara: XID: Don't care identification of test patterns for combinational circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 321-326 (2004) |
2003 | ||
43 | EE | Kohei Miyase, Seiji Kajihara: Optimal Scan Tree Construction with Test Vector Modification for Test Compression. Asian Test Symposium 2003: 136-141 |
42 | EE | Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka: On Estimation of Fault Efficiency for Path Delay Faults. Asian Test Symposium 2003: 64-67 |
41 | EE | Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Chakrabarty: On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume. ICCD 2003: 387-396 |
40 | EE | Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz: A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. ICCD 2003: 397- |
39 | EE | Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz: On test data volume reduction for multiple scan chain designs. ACM Trans. Design Autom. Electr. Syst. 8(4): 460-469 (2003) |
38 | EE | Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara: On Selecting Testable Paths in Scan Designs. J. Electronic Testing 19(4): 447-456 (2003) |
37 | EE | Takeshi Asakawa, Kazuhiko Iwasaki, Seiji Kajihara: BIST-oriented test pattern generator for detection of transition faults. Systems and Computers in Japan 34(3): 76-84 (2003) |
2002 | ||
36 | EE | Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy: Test Data Compression Using Don?t-Care Identification and Statistical Encoding. Asian Test Symposium 2002: 67- |
35 | EE | Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy: A Method of Static Test Compaction Based on Don't Care Identification. DELTA 2002: 392-395 |
34 | EE | Seiji Kajihara, Kenjiro Taniguchi, Irith Pomeranz, Sudhakar M. Reddy: Test Data Compression Using Don't-Care Identification and Statistical Encoding. DELTA 2002: 413-416 |
33 | EE | Kohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy: Don't-Care Identification on Specific Bits of Test Patterns. ICCD 2002: 194-199 |
32 | EE | Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita: On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. ITC 2002: 83-89 |
31 | EE | Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz: On Test Data Volume Reduction for Multiple Scan Chain Designs. VTS 2002: 103-110 |
30 | EE | Seiji Kajihara, Koji Ishida, Kohei Miyase: Test Vector Modification for Power Reduction during Scan Testing. VTS 2002: 160-165 |
2001 | ||
29 | EE | Yun Shao, Sudhakar M. Reddy, Seiji Kajihara, Irith Pomeranz: An Efficient Method to Identify Untestable Path Delay Faults. Asian Test Symposium 2001: 233-238 |
28 | EE | Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara: Hybrid BIST Using Partially Rotational Scan. Asian Test Symposium 2001: 379-384 |
27 | EE | Seiji Kajihara, Kohei Miyase: On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits. ICCAD 2001: 364-369 |
2000 | ||
26 | EE | Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy: Enhanced untestable path analysis using edge graphs. Asian Test Symposium 2000: 139-144 |
25 | Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta: On validating data hold times for flip-flops in sequential circuits. ITC 2000: 317-325 | |
24 | Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy: Selection of potentially testable path delay faults for test generation. ITC 2000: 376-384 | |
1999 | ||
23 | EE | Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara: On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium 1999: 147-152 |
22 | EE | Seiji Kajihara, Atsushi Murakami, Tomohisa Kaneko: On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits. Asian Test Symposium 1999: 20-24 |
21 | EE | Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara: On Test Generation with A Limited Number of Tests. Great Lakes Symposium on VLSI 1999: 12-15 |
1998 | ||
20 | EE | Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita: An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification. Asian Test Symposium 1998: 58-63 |
19 | EE | Seiji Kajihara, Kewal K. Saluja: On Test Pattern Compaction Using Random Pattern Fault Simulation. VLSI Design 1998: 464-469 |
1997 | ||
18 | EE | Seiji Kajihara, Tsutomu Sasao: On the Adders with Minimum Tests. Asian Test Symposium 1997: 10-15 |
17 | EE | Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy: A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. VLSI Design 1997: 82-87 |
16 | EE | Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara: Compact test sets for high defect coverage. IEEE Trans. on CAD of Integrated Circuits and Systems 16(8): 923-930 (1997) |
15 | EE | Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita: Synthesis of Sequential Circuits by Redundancy Removal and Retiming. J. Electronic Testing 11(1): 81-92 (1997) |
14 | EE | Atsushi Yoshikawa, Seiji Kajihara, Masahiro Numa, Kozo Kinoshita: A diagnosis method for single logic design errors in gate-level combinational circuits. Systems and Computers in Japan 28(6): 30-39 (1997) |
13 | EE | Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara: On invariant implication relations for removing partial circuits. Systems and Computers in Japan 28(7): 39-47 (1997) |
1996 | ||
12 | EE | Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. Asian Test Symposium 1996: 94-99 |
11 | EE | Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara: On the effects of test compaction on defect coverage. VTS 1996: 430-437 |
1995 | ||
10 | EE | Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Test sequence compaction by reduced scan shift and retiming. Asian Test Symposium 1995: 169-175 |
9 | Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita: Synthesis for Testability by Sequential Redundancy Removal Using Retiming. FTCS 1995: 33-40 | |
8 | EE | Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita: Resynthesis for sequential circuits designed with a specified initial state. VTS 1995: 152-157 |
7 | EE | Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara: Compact test generation for bridging faults under I/sub DDQ/ testing. VTS 1995: 310-316 |
6 | EE | Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy: Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1496-1504 (1995) |
5 | EE | Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Partial scan design and test sequence generation based on reduced scan shift method. J. Electronic Testing 7(1-2): 115-124 (1995) |
1994 | ||
4 | Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita: Reduced Scan Shift: A New Testing Method for Sequential Circuit. ITC 1994: 624-630 | |
1993 | ||
3 | EE | Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy: Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. DAC 1993: 102-106 |
2 | EE | Seiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita: Test generation for multiple faults based on parallel vector pair analysis. ICCAD 1993: 436-439 |
1992 | ||
1 | Seiji Kajihara, Haruko Shiba, Kozo Kinoshita: Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults. FTCS 1992: 263-270 |