| 2002 |
|---|
| 5 | EE | Jayasanker Jayabalan,
Juraj Povazanec:
Integration of SRAM Redundancy into Production Test.
ITC 2002: 187-193 |
| 2001 |
|---|
| 4 | EE | Oliver Chiu-sing Choy,
Jan Butas,
Juraj Povazanec,
Cheong-fat Chan:
A New Control Circuit for Asynchronous Micropipelines.
IEEE Trans. Computers 50(9): 992-997 (2001) |
| 1999 |
|---|
| 3 | | Juraj Povazanec,
Oliver Chiu-sing Choy,
Cheong-fat Chan,
Jan Butas,
Yeu-qiu Zhang,
Jing-ling Yang,
Tin-yan Tang:
Pipelined Dataflow Architecture of a Small Processor.
PDPTA 1999: 1217-1223 |
| 1998 |
|---|
| 2 | EE | Oliver Chiu-sing Choy,
Tin-chak Pang,
Juraj Povazanec,
Cheong-fat Chan:
A Useful Micropipeline Architecture to Implement DSP Algorithms.
EUROMICRO 1998: 10212- |
| 1997 |
|---|
| 1 | | Juraj Povazanec,
Vladislav Musil:
Fault and test-process modelling for integrated circuits.
Journal of Systems Architecture 43(1-5): 123-127 (1997) |
