| 2009 |
|---|
| 56 | EE | Khawla Alzoubi,
Daniel G. Saab,
Massood Tabib-Azar:
Complementary nano-electromechanical switches for ultra-low power embedded processors.
ACM Great Lakes Symposium on VLSI 2009: 309-314 |
| 2007 |
|---|
| 55 | EE | Jen-Chieh Ou,
Daniel G. Saab,
Qiang Qiang,
Jacob A. Abraham:
Reducing verification overhead with RTL slicing.
ACM Great Lakes Symposium on VLSI 2007: 399-404 |
| 54 | EE | Swarup Bhunia,
Massood Tabib-Azar,
Daniel G. Saab:
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches.
ASP-DAC 2007: 86-91 |
| 53 | | Jason Meyer,
Fatih Kocan,
Daniel G. Saab:
Critical Path Delay Reduction in FPGAs with Unbalanced Lookup Times.
ERSA 2007: 182-190 |
| 52 | EE | Sankar Gurumurthy,
Ramtilak Vemu,
Jacob A. Abraham,
Daniel G. Saab:
Automatic Generation of Instructions to Robustly Test Delay Defects in Processors.
European Test Symposium 2007: 173-178 |
| 51 | EE | Jacob A. Abraham,
Daniel G. Saab:
Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs.
VLSI Design 2007: 6 |
| 50 | EE | Fatih Kocan,
Daniel G. Saab:
Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware.
J. Electronic Testing 23(5): 405-420 (2007) |
| 2006 |
|---|
| 49 | EE | Qiang Qiang,
Daniel G. Saab,
Jacob A. Abraham:
Checking Nested Properties Using Bounded Model Checking and Sequential ATPG.
VLSI Design 2006: 225-230 |
| 2005 |
|---|
| 48 | | Qiang Qiang,
Daniel G. Saab,
Jacob A. Abraham:
An Emulation Model for Sequential ATPG-Based Bounded Model Checking.
FPL 2005: 469-474 |
| 47 | EE | Qiang Qiang,
Chia-Lun Chang,
Daniel G. Saab,
Jacob A. Abraham:
Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core.
ICCD 2005: 461-463 |
| 2003 |
|---|
| 46 | EE | Daniel G. Saab,
Jacob A. Abraham,
Vivekananda M. Vedula:
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines.
VLSI Design 2003: 243-248 |
| 2002 |
|---|
| 45 | EE | Daniel G. Saab,
Fatih Kocan,
Jacob A. Abraham:
Massively Parallel/Reconfigurable Emulation Model for the D-algorithm.
FPL 2002: 1172-1176 |
| 44 | EE | Jacob A. Abraham,
Vivekananda M. Vedula,
Daniel G. Saab:
Verifying Properties Using Sequential ATPG.
ITC 2002: 194-202 |
| 43 | EE | Fatih Kocan,
Daniel G. Saab:
Correction to "ATPG for combinational circuits on configurable hardware".
IEEE Trans. VLSI Syst. 10(3): 374-374 (2002) |
| 2001 |
|---|
| 42 | EE | Fatih Kocan,
Daniel G. Saab:
ATPG for combinational circuits on configurable hardware.
IEEE Trans. VLSI Syst. 9(1): 117-129 (2001) |
| 2000 |
|---|
| 41 | EE | Raghuram S. Tupuri,
Jacob A. Abraham,
Daniel G. Saab:
Hierarchical Test Generation for Systems On a Chip.
VLSI Design 2000: 198- |
| 1999 |
|---|
| 40 | EE | Miron Abramovici,
José T. de Sousa,
Daniel G. Saab:
A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware.
DAC 1999: 684-690 |
| 39 | EE | Fatih Kocan,
Daniel G. Saab:
Dynamic Fault Diagnosis on Reconfigurable Hardware.
DAC 1999: 691-696 |
| 38 | EE | Fatih Kocan,
Daniel G. Saab:
Concurrent D-algorithm on reconfigurable hardware.
ICCAD 1999: 152-156 |
| 37 | EE | Ben Mathew,
Daniel G. Saab:
Combining multiple DFT schemes with test generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 685-696 (1999) |
| 1998 |
|---|
| 36 | EE | Jalal A. Wehbeh,
Daniel G. Saab:
Initialization of Sequential Circuits and its Application to ATPG.
J. Electronic Testing 13(3): 259-271 (1998) |
| 1997 |
|---|
| 35 | | Miron Abramovici,
Daniel G. Saab:
Satisfiability on reconfigurable hardware.
FPL 1997: 448-456 |
| 1996 |
|---|
| 34 | EE | Jalal A. Wehbeh,
Daniel G. Saab:
Initialization of sequential circuits and its application to ATPG.
VTS 1996: 246-253 |
| 33 | EE | Daniel G. Saab,
Youssef Saab,
Jacob A. Abraham:
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1278-1285 (1996) |
| 32 | | Antoine N. Mourad,
W. Kent Fuchs,
Daniel G. Saab:
Site Partitioning for Redundant Arrays of Distributed Disks.
J. Parallel Distrib. Comput. 33(1): 1-11 (1996) |
| 1995 |
|---|
| 31 | | Ben Mathew,
Daniel G. Saab:
DFT & ATPG: Together Again.
ITC 1995: 262-271 |
| 1994 |
|---|
| 30 | | Elizabeth M. Rudnick,
John G. Holm,
Daniel G. Saab,
Janak H. Patel:
Application of Simple Genetic Algorithms to Sequential Circuit Test Generation.
EDAC-ETC-EUROASIC 1994: 40-45 |
| 29 | EE | Daniel G. Saab,
Youssef Saab,
Jacob A. Abraham:
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0.
ICCAD 1994: 40-43 |
| 28 | | Jalal A. Wehbeh,
Daniel G. Saab:
On the Initialization of Sequential Circuits.
ITC 1994: 233-239 |
| 27 | EE | Chung-Hsing Chen,
Tanay Karnik,
Daniel G. Saab:
Structural and behavioral synthesis for testability techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(6): 777-785 (1994) |
| 1993 |
|---|
| 26 | EE | Gwan S. Choi,
Ravishankar K. Iyer,
Daniel G. Saab:
Fault behavior dictionary for simulation of device-level transients.
ICCAD 1993: 6-9 |
| 25 | EE | Ben Mathew,
Daniel G. Saab:
Augmented partial reset.
ICCAD 1993: 716-719 |
| 24 | | Antoine N. Mourad,
W. Kent Fuchs,
Daniel G. Saab:
Performance of Redundant Disk Array Organizations in Transaction Processing Environments.
ICPP 1993: 138-145 |
| 23 | | Antoine N. Mourad,
W. Kent Fuchs,
Daniel G. Saab:
Assigning Sites fto Redundant Clusters in a Distributed Storage System.
ICPP 1993: 64-71 |
| 22 | | Miron Abramovici,
Prashant S. Parikh,
Ben Mathew,
Daniel G. Saab:
On Selecting Flip-Flops for Partial Reset.
ITC 1993: 1008-1012 |
| 21 | | Praveen Vishakantaiah,
Jacob A. Abraham,
Daniel G. Saab:
CHEETA: Composition of Hierarchical Sequential Tests Using ATKET.
ITC 1993: 606-615 |
| 20 | EE | Robert B. Mueller-Thuns,
Daniel G. Saab,
Robert F. Damiano,
Jacob A. Abraham:
Benchmarking Parallel Processing Platforms: An Applications Perspective.
IEEE Trans. Parallel Distrib. Syst. 4(8): 947-954 (1993) |
| 19 | EE | Daniel G. Saab:
Parallel-concurrent fault simulation.
IEEE Trans. VLSI Syst. 1(3): 356-364 (1993) |
| 18 | EE | Chung-Hsing Chen,
Daniel G. Saab:
A novel behavioral testability measure.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(12): 1960-1970 (1993) |
| 17 | EE | Robert B. Mueller-Thuns,
Daniel G. Saab,
Robert F. Damiano,
Jacob A. Abraham:
VLSI logic and fault simulation on general-purpose parallel computers.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(3): 446-460 (1993) |
| 16 | EE | Andrew T. Yang,
Yu-Hsu Chang,
Daniel G. Saab,
Ibrahim N. Hajj:
Switch-level timing simulation of bipolar ECL circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(4): 516-530 (1993) |
| 15 | | Antoine N. Mourad,
W. Kent Fuchs,
Daniel G. Saab:
Recovery Issues in Databases Using Redundant Disk Arrays.
J. Parallel Distrib. Comput. 17(1-2): 75-89 (1993) |
| 1992 |
|---|
| 14 | EE | Daniel G. Saab,
Youssef Saab,
Jacob A. Abraham:
CRIS: a test cultivation program for sequential VLSI circuits.
ICCAD 1992: 216-219 |
| 13 | EE | Chung-Hsing Chen,
Daniel G. Saab:
Behavioral synthesis for testability.
ICCAD 1992: 612-615 |
| 12 | | Jalal A. Wehbeh,
Daniel G. Saab:
Hierarchical Simulation of MOS Circuits Using Extracted Functional Models.
ICCD 1992: 512-515 |
| 11 | EE | Antoine N. Mourad,
W. Kent Fuchs,
Daniel G. Saab:
Database Recovery Using Redundant Disk Arrays.
ICDE 1992: 176-183 |
| 10 | | Antoine N. Mourad,
W. Kent Fuchs,
Daniel G. Saab:
Site Partitioning for Distributed Redundant Disk Arrays.
RIDE-TQP 1992: 214 |
| 1991 |
|---|
| 9 | | Chung-Hsing Chen,
Chienwen Wu,
Daniel G. Saab:
BETA: Behavioral Testability Analysis.
ICCAD 1991: 202-205 |
| 8 | | Chung-Hsing Chen,
Chienwen Wu,
Daniel G. Saab:
Accessibility Analysis on Data Flow Graph: An Approach to Design for Testability.
ICCD 1991: 463-466 |
| 1990 |
|---|
| 7 | EE | David T. Blaauw,
Daniel G. Saab,
Junsheng Long,
Jacob A. Abraham:
Derivation of signal flow for switch-level simulation.
EURO-DAC 1990: 301-305 |
| 6 | | David Blaauw,
Robert B. Mueller-Thuns,
Daniel G. Saab,
Prithviraj Banerjee,
Jacob A. Abraham:
SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction.
ICCAD 1990: 66-69 |
| 5 | EE | Robert B. Mueller-Thuns,
Daniel G. Saab,
Jacob A. Abraham:
Design of a scalable parallel switch-level simulator for VLSI.
SC 1990: 615-624 |
| 4 | EE | Daniel G. Saab,
Robert B. Mueller-Thuns,
David Blaauw,
Joseph T. Rahmeh,
Jacob A. Abraham:
Hierarchical multi-level fault simulation of large systems.
J. Electronic Testing 1(2): 139-149 (1990) |
| 1989 |
|---|
| 3 | EE | David Blaauw,
Daniel G. Saab,
Robert B. Mueller-Thuns,
Jacob A. Abraham,
Joseph T. Rahmeh:
Automatic Generation of Behavioral Models from Switch-Level Descriptions.
DAC 1989: 179-184 |
| 1988 |
|---|
| 2 | EE | Daniel G. Saab,
Andrew T. Yang,
Ibrahim N. Hajj:
Delay Modeling and Time of Bipolar Digital Circuits.
DAC 1988: 288-293 |
| 1987 |
|---|
| 1 | EE | Ibrahim N. Hajj,
Daniel G. Saab:
Switch-Level Logic Simulation of Digital Bipolar Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(2): 251-258 (1987) |
