| |
| 2002 | ||
|---|---|---|
| 4 | EE | Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar: A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC? Chip Multi-Processors. ITC 2002: 726-735 |
| 2001 | ||
| 3 | Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar: Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors. ICCD 2001: 526-529 | |
| 1999 | ||
| 2 | Thomas A. Ziaja: Using LSSD to test modules at the board level. ITC 1999: 163-170 | |
| 1994 | ||
| 1 | EE | Thomas A. Ziaja, Earl E. Swartzlander Jr.: Boundary scan in board manufacturing. J. Electronic Testing 5(2-3): 263-268 (1994) |
| 1 | Anand D'Souza | [4] |
| 2 | Amitava Majumdar | [3] [4] |
| 3 | Ishwar Parulkar | [4] |
| 4 | Rajesh Pendurkar | [4] |
| 5 | Earl E. Swartzlander Jr. | [1] |
| 6 | Kamran Zarrineh | [3] |