Masakatsu Suda

List of publications from the DBLP Bibliography Server - FAQ

2004

2 EE Daisuke Watanabe, Masakatsu Suda, Toshiyuki Okayasu: 34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System. ITC 2004: 1255-1262

2002

1 EE Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto: CMOS Circuit Technology for Precise GHz Timing Generator. ITC 2002: 894-902

2004
2	EE	Daisuke Watanabe, Masakatsu Suda, Toshiyuki Okayasu: 34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System. ITC 2004: 1255-1262
2002
1	EE	Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto: CMOS Circuit Technology for Precise GHz Timing Generator. ITC 2002: 894-902

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