Tapan J. Chakraborty

2008
20	EE	Aditya Jagirdar, Roystein Oliveira, Tapan J. Chakraborty: A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits. VLSI Design 2008: 39-44
2007
19	EE	Roystein Oliveira, Aditya Jagirdar, Tapan J. Chakraborty: A TMR Scheme for SEU Mitigation in Scan Flip-Flops. ISQED 2007: 905-910
18		Brendan Mullane, Chen-Huan Chiang, Michael Higgins, Ciaran MacNamee, Tapan J. Chakraborty, Thomas B. Cook: FPGA Prototyping of a Scan Based System-On-Chip Design. ReCoSoC 2007: 121-126
2005
17	EE	Tapan J. Chakraborty: Efficient Test Architecture based on Boundary Scan for Comprehensive System Test. Asian Test Symposium 2005: 464-465
2002
16	EE	Tapan J. Chakraborty, Chen-Huan Chiang: A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur. ITC 2002: 923-929
2000
15	EE	Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: Path delay fault simulation of sequential circuits. IEEE Trans. VLSI Syst. 8(2): 223-228 (2000)
14	EE	Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: Improving path delay testability of sequential circuits. IEEE Trans. VLSI Syst. 8(6): 736-741 (2000)
1998
13	EE	Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik: A BIST scheme for the detection of path-delay faults. ITC 1998: 422-
1997
12		Tapan J. Chakraborty, Vishwani D. Agrawal: Effective Path Selection for Delay Fault Testing of Sequential Circuits. ITC 1997: 998-1003
11	EE	Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: On variable clock methods for path delay testing of sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1237-1249 (1997)
1996
10	EE	Tapan J. Chakraborty, Vishwani D. Agrawal: Design for high-speed testability of stuck-at faults. VLSI Design 1996: 53-56
1995
9		Vishwani D. Agrawal, Tapan J. Chakraborty: High-Performance Circuit Testing with Slow-Speed Testers. ITC 1995: 302-310
8	EE	Tapan J. Chakraborty, Vishwani D. Agrawal: Robust testing for stuck-at faults. VLSI Design 1995: 42-46
7	EE	Tapan J. Chakraborty, Vishwani D. Agrawal: Simulation of at-speed tests for stuck-at faults. VTS 1995: 216-220
1993
6	EE	Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: Design for Testability for Path Delay faults in Sequential Circuits. DAC 1993: 453-457
1992
5	EE	Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: Delay Fault Models and Test Generation for Random Logic Sequential Circuits. DAC 1992: 165-172
1991
4	EE	Tapan J. Chakraborty, Sudipta Bhawmik, Robert Bencivenga, Chih-Jen Lin: Enhanced Controllability for IDDQ Test Sets Using Partial Scan. DAC 1991: 278-281
3	EE	Sumit Ghosh, Tapan J. Chakraborty: On behavior fault modeling for digital designs. J. Electronic Testing 2(2): 135-151 (1991)
1989
2		Wu-Tung Cheng, Tapan J. Chakraborty: Gentest: An Automatic Test-Generation System for Sequential Circuits. IEEE Computer 22(4): 43-49 (1989)
1988
1		Tapan J. Chakraborty, Sumit Ghosh: On Behavior Fault Modeling for Combinational Digital Designs. ITC 1988: 593-600

Coauthor Index

1	Vishwani D. Agrawal	[5] [6] [7] [8] [9] [10] [11] [12] [14] [15]
2	Robert Bencivenga	[4]
3	Sudipta Bhawmik	[4] [13]
4	Michael L. Bushnell	[5] [6] [11] [14] [15]
5	Wu-Tung Cheng	[2]
6	Chen-Huan Chiang	[16] [18]
7	Thomas B. Cook	[18]
8	Sumit Ghosh	[1] [3]
9	Michael Higgins	[18]
10	Aditya Jagirdar	[19] [20]
11	Chih-Jen Lin	[4]
12	Ciaran MacNamee	[18]
13	Nilanjan Mukherjee	[13]
14	Brendan Mullane	[18]
15	Roystein Oliveira	[19] [20]

Colors in the list of coauthors