2009 | ||
---|---|---|
71 | EE | Miad Faezipour, Mehrdad Nourani: Wire-Speed TCAM-Based Architectures for Multimatch Packet Classification. IEEE Trans. Computers 58(1): 5-17 (2009) |
2008 | ||
70 | EE | Miad Faezipour, Mehrdad Nourani: Reconfigurable Constraint Repetition Unit for Regular Expression Matching. FCCM 2008: 279-280 |
69 | EE | Miad Faezipour, Mehrdad Nourani: Regular Expression Matching for Reconfigurable Constraint Repetition Inspection. GLOBECOM 2008: 2094-2098 |
68 | EE | Miad Faezipour, Mehrdad Nourani: Constraint Repetition Inspection for Regular Expression on FPGA. Hot Interconnects 2008: 111-118 |
67 | EE | Ali Namazi, S. Askari, Mehrdad Nourani: Highly reliable A/D converter using analog voting. ICCD 2008: 334-339 |
66 | EE | Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed: Low-Transition Test Pattern Generation for BIST-Based Applications. IEEE Trans. Computers 57(3): 303-315 (2008) |
2007 | ||
65 | EE | Ali Namazi, Mehrdad Nourani: Distributed voting for fault-tolerant nanoscale systems. ICCD 2007: 568-573 |
64 | EE | Mohammad J. Akhbarizadeh, Mehrdad Nourani, Rina Panigrahy, Samar Sharma: A TCAM-Based Parallel Architecture for High-Speed Packet Forwarding. IEEE Trans. Computers 56(1): 58-72 (2007) |
63 | EE | A. Amirabadi, Ali Afzali-Kusha, Y. Mortazavi, Mehrdad Nourani: Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper. IEEE Trans. VLSI Syst. 15(2): 125-134 (2007) |
2006 | ||
62 | EE | Miad Faezipour, Mehrdad Nourani: A Customized TCAM Architecture for Multi-Match Packet Classification. GLOBECOM 2006 |
61 | EE | Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara: Reconfigurable CAM Architecture for Network Search Engines. ICCD 2006 |
60 | EE | Mehrdad Nourani, Arun Radhakrishnan: Testing On-Die Process Variation in Nanometer VLSI. IEEE Design & Test of Computers 23(6): 438-451 (2006) |
59 | EE | Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, T. Balsara: A nonredundant ternary CAM circuit for network search engines. IEEE Trans. VLSI Syst. 14(3): 268-278 (2006) |
2005 | ||
58 | EE | Mohammad Tehranipoor, Mehrdad Nourani, Nisar Ahmed: Low Transition LFSR for BIST-Based Applications. Asian Test Symposium 2005: 138-143 |
57 | EE | Mohammad J. Akhbarizadeh, Mehrdad Nourani, Rina Panigrahy, Samar Sharma: High-Speed and Low-Power Network Search Engine Using Adaptive Block-Selection Scheme. Hot Interconnects 2005: 73-78 |
56 | EE | Deepak S. Vijayasarathi, Mehrdad Nourani, Mohammad J. Akhbarizadeh, Poras T. Balsara: Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines. ICCD 2005: 243-248 |
55 | EE | A. Amirabadi, Y. Mortazavi, Nariman Moezzi Madani, Ali Afzali-Kusha, Mehrdad Nourani: Domino logic with an efficient variable threshold voltage keeper. ISCAS (2) 2005: 1674-1677 |
54 | EE | Morteza Gholipour, Hamid Shojaee, Ali Afzali-Kusha, Ahmad Khademzadeh, Mehrdad Nourani: An efficient model for performance analysis of asynchronous pipeline design methods. ISCAS (5) 2005: 5234-5237 |
53 | EE | Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed: Pattern Generation and Estimation for Power Supply Noise Analysis. VTS 2005: 439-444 |
52 | EE | Mehrdad Nourani, Mohammad H. Tehranipour: RL-huffman encoding for test compression and power reduction in scan applications. ACM Trans. Design Autom. Electr. Syst. 10(1): 91-115 (2005) |
51 | EE | Mohammad J. Akhbarizadeh, Mehrdad Nourani, Cyrus D. Cantrell: Prefix Segregation Scheme for a TCAM-Based IP Forwarding Engine. IEEE Micro 25(4): 48-63 (2005) |
50 | EE | James Chin, Mehrdad Nourani: FITS: An Integrated ILP-Based Test Scheduling Environment. IEEE Trans. Computers 54(12): 1598-1613 (2005) |
49 | EE | Mohammad Tehranipoor, Mehrdad Nourani, Krishnendu Chakrabarty: Nine-coded compression technique for testing embedded cores in SoCs. IEEE Trans. VLSI Syst. 13(6): 719-731 (2005) |
48 | EE | Mohammad J. Akhbarizadeh, Mehrdad Nourani: Hardware-based IP routing using partitioned lookup table. IEEE/ACM Trans. Netw. 13(4): 769-781 (2005) |
47 | EE | Behnam Robatmili, Nasser Yazdani, Mehrdad Nourani: Optimizing SMT processors for IP-packet processing. Microprocessors and Microsystems 29(7): 337-349 (2005) |
2004 | ||
46 | EE | A. Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz: Leakage current reduction by new technique in standby mode. ACM Great Lakes Symposium on VLSI 2004: 158-161 |
45 | EE | Mohammad H. Tehranipour, Mehrdad Nourani, Krishnendu Chakrabarty: Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression. DATE 2004: 1284-1289 |
44 | EE | James Chin, Mehrdad Nourani: SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance. DATE 2004: 710-711 |
43 | EE | Mohammad J. Akhbarizadeh, Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara: PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks. ICCD 2004: 6-11 |
42 | Behnam Robatmili, Nasser Yazdani, Mehrdad Nourani: NPSMT: A Simulation Environment for SMT Packet Processors. ISCA PDCS 2004: 151-156 | |
41 | Mohammad H. Tehranipour, Mehrdad Nourani, Karim Arabi, Ali Afzali-Kusha: Mixed RL-Huffman encoding for power reduction and data compression in scan test. ISCAS (2) 2004: 681-684 | |
40 | Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nourani: Low power pattern generation for BIST architecture. ISCAS (2) 2004: 689-692 | |
39 | Nisar Ahmed, Mohammad H. Tehranipour, Dian Zhou, Mehrdad Nourani: Frequency driven repeater insertion for deep submicron. ISCAS (5) 2004: 181-184 | |
38 | Ali Abbasian, Safar Hatami, Ali Afzali-Kusha, Mehrdad Nourani, Caro Lucas: Event-driven dynamic power management based on wavelet forecasting theory. ISCAS (5) 2004: 325-328 | |
37 | EE | Kendrick Baker, Mehrdad Nourani: Interconnect Test Pattern Generation Algorithm For Meeting Device and Global SSO Limits With Safe Initial Vectors. ITC 2004: 163-172 |
36 | EE | Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani: Testing SoC interconnects for signal integrity using extended JTAG architecture. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 800-811 (2004) |
2003 | ||
35 | EE | Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nourani: Extending JTAG for Testing Signal Integrity in SoCs. DATE 2003: 10218-10223 |
34 | EE | Mehrdad Nourani, James Chin: Power-Time Tradeoff in Test Scheduling for SoCs. ICCD 2003: 548-553 |
33 | EE | Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani: Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity. ICCD 2003: 554- |
32 | EE | Ali Abbasian, S. H. Rasouli, Ali Afzali-Kusha, Mehrdad Nourani: No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications. ISCAS (5) 2003: 289-292 |
31 | EE | Mohammad H. Tehranipour, Mehrdad Nourani, Seid Mehdi Fakhraie, Ali Afzali-Kusha: Systematic test program generation for SoC testing using embedded processor. ISCAS (5) 2003: 541-544 |
30 | EE | Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani: Testing SoC Interconnects for Signal Integrity Using Boundary Scan. VTS 2003: 158-172 |
29 | EE | Mehrdad Nourani, Mohammad J. Akhbarizadeh: Reconfigurable memory architecture for scalable IP forwarding engines. Microprocessors and Microsystems 27(5-6): 253-263 (2003) |
2002 | ||
28 | EE | Amir Attarha, Mehrdad Nourani: Signal integrity fault analysis using reduced-order modeling. DAC 2002: 367-370 |
27 | EE | Mohammad H. Tehranipour, Mehrdad Nourani: Signal Integrity Loss in SoC's Interconnects: A Diagnosis Approach Using Embedded Microprocessor. ITC 2002: 1093-1102 |
26 | EE | Mehrdad Nourani, James Chin: Testing High-Speed SoCs Using Low-Speed ATEs. VTS 2002: 133-138 |
25 | EE | Amir Attarha, Mehrdad Nourani: Test Pattern Generation for Signal Integrity Faults on Long Interconnects. VTS 2002: 336-344 |
24 | EE | Mehrdad Nourani, Christos A. Papachristou: False path exclusion in delay analysis of RTL structures. IEEE Trans. VLSI Syst. 10(1): 30-43 (2002) |
23 | EE | Mehrdad Nourani, Amir Attarha: Signal Integrity: Fault Modeling and Testing in High-Speed SoCs. J. Electronic Testing 18(4-5): 539-554 (2002) |
2001 | ||
22 | EE | Mehrdad Nourani, Amir Attarha: Built-In Self-Test for Signal Integrity. DAC 2001: 792-797 |
21 | Amir Attarha, Mehrdad Nourani: Testing interconnects for noise and skew in gigahertz SoCs. ITC 2001: 305-314 | |
20 | EE | Amir Attarha, Mehrdad Nourani: Built-In-Chip Testing of Voltage Overshoots in High-Speed SoCs. VTS 2001: 111-116 |
19 | EE | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou: Integrated test of interacting controllers and datapaths. ACM Trans. Design Autom. Electr. Syst. 6(3): 401-422 (2001) |
2000 | ||
18 | EE | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou: Synthesis-for-testability of controller-datapath pairs that use gated clocks. DAC 2000: 613-618 |
17 | EE | Amir Attarha, Mehrdad Nourani, Caro Lucas: Modeling and simulation of real defects using fuzzy logic. DAC 2000: 631-636 |
16 | EE | Joan Carletta, Christos A. Papachristou, Mehrdad Nourani: Detecting Undetectable Controller Faults Using Power Analysis. DATE 2000: 723-728 |
15 | Mehrdad Nourani, Christos A. Papachristou: An ILP formulation to optimize test access mechanism in system-on-chip testing. ITC 2000: 902-910 | |
14 | EE | Mehrdad Nourani, Christos A. Papachristou: Stability-based algorithms for high-level synthesis of digital ASICs. IEEE Trans. VLSI Syst. 8(4): 431-435 (2000) |
1999 | ||
13 | EE | Christos A. Papachristou, F. Martin, Mehrdad Nourani: Microprocessor Based Testing for Core-Based System on Chip. DAC 1999: 586-591 |
12 | EE | Joan Carletta, Mehrdad Nourani, Christos A. Papachristou: Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs. DATE 1999: 278-282 |
11 | EE | Christos A. Papachristou, Mehrdad Nourani, Mark Spining: A multiple clocking scheme for low-power RTL design. IEEE Trans. VLSI Syst. 7(2): 266-276 (1999) |
10 | EE | Mehrdad Nourani, Christos A. Papachristou: Structural Fault Testing of Embedded Cores Using Pipelining. J. Electronic Testing 15(1-2): 129-144 (1999) |
1998 | ||
9 | EE | Mehrdad Nourani, Christos A. Papachristou: A Bypass Scheme for Core-Based System Fault Testing. DATE 1998: 979-980 |
8 | EE | Mehrdad Nourani, Christos A. Papachristou: Parallelism in Structural Fault Testing of Embedded Cores. VTS 1998: 15-21 |
1997 | ||
7 | EE | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou: A Scheme for Integrated Controller-Datapath Fault Testing. DAC 1997: 546-551 |
6 | EE | Mehrdad Nourani, Christos A. Papachristou: Structural BIST insertion using behavioral test analysis. ED&TC 1997: 64-68 |
1996 | ||
5 | EE | Christos A. Papachristou, Mark Spining, Mehrdad Nourani: An Effective Power Management Scheme for RTL Design Based on Multiple Clocks. DAC 1996: 337-342 |
1995 | ||
4 | EE | Christos A. Papachristou, Mark Spining, Mehrdad Nourani: A multiple clocking scheme for low power RTL design. ISLPD 1995: 27-32 |
1993 | ||
3 | EE | Mehrdad Nourani, Christos A. Papachristou: A Layout Estimation Algorithm for RTL Datapaths. DAC 1993: 285-291 |
2 | EE | Christos A. Papachristou, Haidar Harmanani, Mehrdad Nourani: An Approach for Redesigning in Data Path Synthesis. DAC 1993: 419-423 |
1992 | ||
1 | EE | Mehrdad Nourani, Christos A. Papachristou: Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital Systems. DAC 1992: 99-105 |