| 2008 |
|---|
| 114 | EE | Zhaoliang Pan,
Melvin A. Breuer:
Basing Acceptable Error-Tolerant Performance on Significance-Based Error-rate (SBER).
VTS 2008: 59-66 |
| 113 | EE | Melvin A. Breuer,
Haiyang (Henry) Zhu:
An Illustrated Methodology for Analysis of Error Tolerance.
IEEE Design & Test of Computers 25(2): 168-177 (2008) |
| 112 | EE | Tong-Yu Hsieh,
Kuen-Jong Lee,
Melvin A. Breuer:
An Error Rate Based Test Methodology to Support Error-Tolerance.
IEEE Transactions on Reliability 57(1): 204-214 (2008) |
| 2007 |
|---|
| 111 | EE | Tong-Yu Hsieh,
Kuen-Jong Lee,
Melvin A. Breuer:
Reduction of detected acceptable faults for yield improvement via error-tolerance.
DATE 2007: 1599-1604 |
| 110 | EE | Zhaoliang Pan,
Melvin A. Breuer:
Estimating Error Rate in Defective Logic Using Signature Analysis.
IEEE Trans. Computers 56(5): 650-661 (2007) |
| 2006 |
|---|
| 109 | EE | Shahin Nazarian,
Massoud Pedram,
Sandeep K. Gupta,
Melvin A. Breuer:
STAX: statistical crosstalk target set compaction.
DATE Designers' Forum 2006: 172-177 |
| 108 | EE | Melvin A. Breuer,
Haiyang (Henry) Zhu:
Error-Tolerance and Multi-Media.
IIH-MSP 2006: 521-524 |
| 107 | EE | Tong-Yu Hsieh,
Kuen-Jong Lee,
Melvin A. Breuer:
An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance.
VTS 2006: 130-135 |
| 2005 |
|---|
| 106 | EE | Melvin A. Breuer:
Multi-media Applications and Imprecise Computation.
DSD 2005: 2-7 |
| 105 | EE | Melvin A. Breuer:
Let's Think Analog.
ISVLSI 2005: 2-5 |
| 2004 |
|---|
| 104 | EE | Melvin A. Breuer,
Sandeep K. Gupta,
Shahin Nazarian:
Efficient Identification of Crosstalk Induced Slowdown Targets.
Asian Test Symposium 2004: 124-131 |
| 103 | EE | Melvin A. Breuer:
Intelligible Test Techniques to Support Error-Tolerance.
Asian Test Symposium 2004: 386-393 |
| 102 | EE | Lei Wang,
Sandeep K. Gupta,
Melvin A. Breuer:
Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects.
Asian Test Symposium 2004: 440-447 |
| 101 | EE | Melvin A. Breuer:
Determining error rate in error tolerant VLSI chips.
DELTA 2004: 321-326 |
| 100 | EE | Shahdad Irajpour,
Sandeep K. Gupta,
Melvin A. Breuer:
Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models.
ITC 2004: 1024-1033 |
| 99 | EE | Melvin A. Breuer,
Sandeep K. Gupta,
T. M. Mak:
Defect and Error Tolerance in the Presence of Massive Numbers of Defects.
IEEE Design & Test of Computers 21(3): 216-227 (2004) |
| 2003 |
|---|
| 98 | EE | Arani Sinha,
Sandeep K. Gupta,
Melvin A. Breuer:
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults.
Asian Test Symposium 2003: 174-177 |
| 97 | EE | Yi-Shing Chang,
Sandeep K. Gupta,
Melvin A. Breuer:
Test Generation for Maximizing Ground Bounce Considering Circuit Delay.
VTS 2003: 151-157 |
| 96 | EE | Shahdad Irajpour,
Shahin Nazarian,
Lei Wang,
Sandeep K. Gupta,
Melvin A. Breuer:
Analyzing Crosstalk in the Presence of Weak Bridge Defects.
VTS 2003: 385-392 |
| 2002 |
|---|
| 95 | EE | I-De Huang,
Sandeep K. Gupta,
Melvin A. Breuer:
Accurate and Efficient Static Timing Analysis with Crosstalk.
ICCD 2002: 265-272 |
| 94 | EE | Shahin Nazarian,
Hang Huang,
Suriyaprakash Natarajan,
Sandeep K. Gupta,
Melvin A. Breuer:
XIDEN: Crosstalk Target Identification Framework.
ITC 2002: 365-374 |
| 93 | EE | Wei-Yu Chen,
Sandeep K. Gupta,
Melvin A. Breuer:
Analytical models for crosstalk excitation and propagation in VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1117-1131 (2002) |
| 92 | EE | Wei-Yu Chen,
Sandeep K. Gupta,
Melvin A. Breuer:
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results.
J. Electronic Testing 18(1): 17-28 (2002) |
| 91 | EE | Liang-Chi Chen,
Sandeep K. Gupta,
Melvin A. Breuer:
TA-PSV - Timing Analysis for Partially Specified Vectors.
J. Electronic Testing 18(1): 73-88 (2002) |
| 2001 |
|---|
| 90 | EE | Liang-Chi Chen,
Sandeep K. Gupta,
Melvin A. Breuer:
A New Gate Delay Model for Simultaneous Switching and Its Applications.
DAC 2001: 289-294 |
| 89 | | Suriyaprakash Natarajan,
Sandeep K. Gupta,
Melvin A. Breuer:
Switch-level delay test of domino logic circuits.
ITC 2001: 367-376 |
| 88 | | Liang-Chi Chen,
T. M. Mak,
Sandeep K. Gupta,
Melvin A. Breuer:
Crosstalk test generation on pseudo industrial circuits: a case study.
ITC 2001: 548-557 |
| 87 | EE | Yi-Shing Chang,
Sandeep K. Gupta,
Melvin A. Breuer:
Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out.
VTS 2001: 358-367 |
| 86 | EE | Ishwar Parulkar,
Sandeep K. Gupta,
Melvin A. Breuer:
Introducing redundant computations in RTL data paths for reducing BIST resources.
ACM Trans. Design Autom. Electr. Syst. 6(3): 423-445 (2001) |
| 2000 |
|---|
| 85 | EE | Liang-Chi Chen,
Sandeep K. Gupta,
Melvin A. Breuer:
A new framework for static timing analysis, incremental timing refinement, and timing simulation.
Asian Test Symposium 2000: 102-107 |
| 84 | EE | Wei-Yu Chen,
Sandeep K. Gupta,
Melvin A. Breuer:
Test generation for crosstalk-induced faults: framework and computational result.
Asian Test Symposium 2000: 305-310 |
| 83 | EE | Melvin A. Breuer,
Kwang-Ting Cheng:
Challenges for the Academic Test Community.
Asian Test Symposium 2000: 4- |
| 82 | | Melvin A. Breuer,
Sandeep K. Gupta:
New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits.
VLSI Design 2000: 8 |
| 81 | EE | Melvin A. Breuer:
High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability.
VTS 2000: 473-474 |
| 80 | EE | Rajagopalan Srinivasan,
Sandeep K. Gupta,
Melvin A. Breuer:
Novel Test Pattern Generators for Pseudoexhaustive Testing.
IEEE Trans. Computers 49(11): 1228-1240 (2000) |
| 79 | EE | Melvin A. Breuer,
Majid Sarrafzadeh,
Fabio Somenzi:
Fundamental CAD algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(12): 1449-1475 (2000) |
| 1999 |
|---|
| 78 | EE | Arani Sinha,
Sandeep K. Gupta,
Melvin A. Breuer:
Validation and test generation for oscillatory noise in VLSI interconnects.
ICCAD 1999: 289-296 |
| 77 | | Suriyaprakash Natarajan,
Sandeep K. Gupta,
Melvin A. Breuer:
Switch-level delay test.
ITC 1999: 171-180 |
| 76 | | Wei-Yu Chen,
Sandeep K. Gupta,
Melvin A. Breuer:
Test generation for crosstalk-induced delay in integrated circuits.
ITC 1999: 191-200 |
| 75 | EE | Yi-Shing Chang,
Sandeep K. Gupta,
Melvin A. Breuer:
Test Generation for Ground Bounce in Internal Logic Circuitry.
VTS 1999: 95-105 |
| 1998 |
|---|
| 74 | EE | Ishwar Parulkar,
Sandeep K. Gupta,
Melvin A. Breuer:
Introducing Redundant Computations in a Behavior for Reducing BIST Resources.
DAC 1998: 548-553 |
| 73 | EE | Ishwar Parulkar,
Sandeep K. Gupta,
Melvin A. Breuer:
Scheduling and Module Assignment for Reducing Bist Resources.
DATE 1998: 66-73 |
| 72 | EE | Suriyaprakash Natarajan,
Melvin A. Breuer,
Sandeep K. Gupta:
Process Variations and their Impact on Circuit Operation.
DFT 1998: 73- |
| 71 | EE | Weiyu Chen,
Sandeep K. Gupta,
Melvin A. Breuer:
Test generation in VLSI circuits for crosstalk noise.
ITC 1998: 641- |
| 70 | EE | Rajagopalan Srinivasan,
Sandeep K. Gupta,
Melvin A. Breuer:
Bounds on pseudoexhaustive test lengths.
IEEE Trans. VLSI Syst. 6(3): 420-431 (1998) |
| 69 | EE | Ishwar Parulkar,
Sandeep K. Gupta,
Melvin A. Breuer:
Allocation Techniques for Reducing BIST Area Overhead of Data Paths.
J. Electronic Testing 13(2): 149-166 (1998) |
| 68 | EE | Ishwar Parulkar,
Sandeep K. Gupta,
Melvin A. Breuer:
Estimation of BIST Resources During High-Level Synthesis.
J. Electronic Testing 13(3): 221-237 (1998) |
| 67 | EE | Debaditya Mukherjee,
Melvin A. Breuer:
An IEEE 1149.1 Compliant Test Control Architecture.
J. Electronic Testing 13(3): 273-297 (1998) |
| 1997 |
|---|
| 66 | | Weiyu Chen,
Melvin A. Breuer,
Sandeep K. Gupta:
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs.
ITC 1997: 809-818 |
| 65 | EE | Yi-Shing Chang,
Sandeep K. Gupta,
Melvin A. Breuer:
Analysis of Ground Bounce in Deep Sub-Micron Circuits.
VTS 1997: 110-116 |
| 64 | EE | Melvin A. Breuer,
Bozena Kaminska,
J. McDermid,
V. Rayapathi,
Donald L. Wheater:
Will 0.1um Digital Circuits Require Mixed-Signal Testing.
VTS 1997: 186-187 |
| 63 | EE | Liang-Chi Chen,
Sandeep K. Gupta,
Melvin A. Breuer:
High Quality Robust Tests for Path Delay Faults.
VTS 1997: 88-93 |
| 1996 |
|---|
| 62 | EE | Ishwar Parulkar,
Sandeep K. Gupta,
Melvin A. Breuer:
Lower Bounds on Test Resources for Scheduled Data Flow Graphs.
DAC 1996: 143-148 |
| 61 | | Melvin A. Breuer,
Sandeep K. Gupta:
Process-Aggravated Noise (PAN): New Validation and Test Problems.
ITC 1996: 914-923 |
| 1995 |
|---|
| 60 | EE | Ishwar Parulkar,
Sandeep K. Gupta,
Melvin A. Breuer:
Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead.
DAC 1995: 395-401 |
| 59 | EE | Sridhar Narayanan,
Melvin A. Breuer:
Asynchronous multiple scan chain.
VTS 1995: 270-276 |
| 58 | EE | Kuen-Jong Lee,
Chih-Nan Wang,
Rajiv Gupta,
Melvin A. Breuer:
An integrated system for assigning signal flow directions to CMOS transistors.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1445-1458 (1995) |
| 57 | EE | Mody Lempel,
Sandeep K. Gupta,
Melvin A. Breuer:
Test embedding with discrete logarithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 554-566 (1995) |
| 56 | EE | Sridhar Narayanan,
Melvin A. Breuer:
Reconfiguration techniques for a single scan chain.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(6): 750-765 (1995) |
| 55 | EE | Rajesh Gupta,
Melvin A. Breuer:
Partial scan design of register-transfer level circuits.
J. Electronic Testing 7(1-2): 25-46 (1995) |
| 1994 |
|---|
| 54 | EE | Ishwar Parulkar,
Melvin A. Breuer,
Charles Njinda:
Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BIST.
DAC 1994: 345-356 |
| 53 | | Sen-Pin Lin,
Sandeep K. Gupta,
Melvin A. Breuer:
A Low Cost BIST Methodology and Associated Novel Test Pattern Generator.
EDAC-ETC-EUROASIC 1994: 106-112 |
| 52 | | Debaditya Mukherjee,
Massoud Pedram,
Melvin A. Breuer:
Control Strategies for Chip-Based DFT/BIST Hardware.
ITC 1994: 893-902 |
| 51 | EE | Kuen-Jong Lee,
Charles Njinda,
Melvin A. Breuer:
SWiTEST: a switch level test generation system for CMOS combinational circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 625-637 (1994) |
| 1993 |
|---|
| 50 | EE | Rajagopalan Srinivasan,
Sandeep K. Gupta,
Melvin A. Breuer:
An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing.
DAC 1993: 242-248 |
| 49 | EE | Sridhar Narayanan,
Melvin A. Breuer:
Reconfigurable scan chains: a novel approach to reduce test application time.
ICCAD 1993: 710-715 |
| 48 | EE | Debaditya Mukherjee,
Massoud Pedram,
Melvin A. Breuer:
Merging multiple FSM controllers for DFT/BIST hardware.
ICCAD 1993: 720-725 |
| 47 | | Rajagopalan Srinivasan,
Sandeep K. Gupta,
Melvin A. Breuer:
Novel Test Pattern Generators for Pseudo-Exhaustive Testing.
ITC 1993: 1041-1050 |
| 46 | | Sridhar Narayanan,
Rajesh Gupta,
Melvin A. Breuer:
Optimal Configuring of Multiple Scan Chains.
IEEE Trans. Computers 42(9): 1121-1131 (1993) |
| 45 | EE | Sen-Pin Lin,
Charles Njinda,
Melvin A. Breuer:
Generating a family of testable designs using the BILBO methodology.
J. Electronic Testing 4(1): 71-89 (1993) |
| 44 | EE | Jung-Cheun Lien,
Melvin A. Breuer:
Test program synthesis for modules and chips having boundary scan.
J. Electronic Testing 4(2): 159-180 (1993) |
| 1992 |
|---|
| 43 | EE | Kuen-Jong Lee,
Charles Njinda,
Melvin A. Breuer:
SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits.
DAC 1992: 26-29 |
| 42 | EE | Sridhar Narayanan,
Rajesh Gupta,
Melvin A. Breuer:
Configuring multiple scan chains for minimum test time.
ICCAD 1992: 4-8 |
| 41 | | Sridhar Narayanan,
Charles Njinda,
Melvin A. Breuer:
Optimal Sequencing of Scan Registers.
ITC 1992: 293-302 |
| 40 | EE | Kuen-Jong Lee,
Melvin A. Breuer:
Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(5): 659-670 (1992) |
| 1991 |
|---|
| 39 | | Debaditya Mukherjee,
Charles Njinda,
Melvin A. Breuer:
Synthesis of Optimal 1-Hot Coded On-Chip Controllers for BIST Hardware.
ICCAD 1991: 236-239 |
| 38 | | Rajesh Gupta,
Melvin A. Breuer:
Ordering Storage Elements in a Single Scan Chain.
ICCAD 1991: 408-411 |
| 37 | | Sen-Pin Lin,
Charles Njinda,
Melvin A. Breuer:
A Systematic Approach for Designing Testable VLSI Circuits.
ICCAD 1991: 496-499 |
| 36 | | Jung-Cheun Lien,
Melvin A. Breuer:
Maximal Diagnosis for Wiring Networks.
ITC 1991: 96-105 |
| 35 | EE | Rajiv Gupta,
Rajagopalan Srinivasan,
Melvin A. Breuer:
Reorganizing Circuits to Aid Testability.
IEEE Design & Test of Computers 8(3): 49-57 (1991) |
| 34 | EE | Asad A. Ismaeel,
Melvin A. Breuer:
The probability of error detection in sequential circuits using random test vectors.
J. Electronic Testing 1(4): 245-256 (1991) |
| 33 | EE | Jung-Cheun Lien,
Melvin A. Breuer:
An optimal scheduling algorithm for testing interconnect using boundary scan.
J. Electronic Testing 2(1): 117-130 (1991) |
| 1990 |
|---|
| 32 | | Kuen-Jong Lee,
Rajiv Gupta,
Melvin A. Breuer:
A New Method for Assigning Signal Flow Directions to MOS Transistors.
ICCAD 1990: 492-495 |
| 31 | | Rajiv Gupta,
Melvin A. Breuer:
An Extensible User Interface for an Object-Oriented VLSI CAD Framework.
ICSI 1990: 559-568 |
| 30 | | A. Majumdar,
C. S. Raghavendra,
Melvin A. Breuer:
Fault Tolerance in Linear Systolic Arrays Using Time Redundancy.
IEEE Trans. Computers 39(2): 269-276 (1990) |
| 29 | | Rajesh Gupta,
Rajiv Gupta,
Melvin A. Breuer:
The BALLAST Methodology for Structured Partial Scan Design.
IEEE Trans. Computers 39(4): 538-544 (1990) |
| 1989 |
|---|
| 28 | | Rajiv Gupta,
Wesley H. Cheng,
Rajesh Gupta,
Ido Hardonag,
Melvin A. Breuer:
An Object-Oriented VLSI CAD Framework: A Case Study in Rapid Prototyping.
IEEE Computer 22(5): 28-37 (1989) |
| 27 | EE | Mandalagiri S. Chandrasekhar,
Melvin A. Breuer:
Optimal routing of two rectangular blocks.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(4): 413-430 (1989) |
| 1988 |
|---|
| 26 | | Sandeep K. Gupta,
Melvin A. Breuer,
Jung-Cheun Lien:
Concurrent Control of Multiple BIT Structures.
ITC 1988: 431-442 |
| 25 | | Melvin A. Breuer,
Jung-Cheun Lien:
A Test and Maintenance Controller for a Module Containing Testable Chips.
ITC 1988: 502-513 |
| 24 | EE | Salim U. Chowdhury,
Melvin A. Breuer:
Optimum design of IC power/ground nets subject to reliability constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(7): 787-796 (1988) |
| 23 | EE | Sarma Sastry,
Melvin A. Breuer:
Detectability of CMOS stuck-open faults using random and pseudorandom test sequences.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(9): 933-946 (1988) |
| 1986 |
|---|
| 22 | | Xi-an Zhu,
Melvin A. Breuer:
A Knowledge-Based TDM Selection System.
FJCC 1986: 854-863 |
| 21 | | Magdy S. Abadir,
Melvin A. Breuer:
Scan Path with Look Ahead Shifting (SPLASH).
ITC 1986: 696-704 |
| 20 | | Melvin A. Breuer,
Asad A. Ismaeel:
Roving Emulation as a Fault Detection Mechanism.
IEEE Trans. Computers 35(11): 933-939 (1986) |
| 19 | | Magdy S. Abadir,
Melvin A. Breuer:
Test Schedules for VLSI Circuits Having Built-In Test Hardware.
IEEE Trans. Computers 35(4): 361-367 (1986) |
| 1985 |
|---|
| 18 | EE | Melvin A. Breuer,
Xi-an Zhu:
A knowledge based system for selecting a test methodology for a PLA.
DAC 1985: 259-265 |
| 17 | EE | Salim U. Chowdhury,
Melvin A. Breuer:
The construction of minimal area power and ground nets for VLSI circuits.
DAC 1985: 794-797 |
| 16 | EE | Ting-Hua Chen,
Melvin A. Breuer:
Automatic Design for Testability Via Testability Measures.
IEEE Trans. on CAD of Integrated Circuits and Systems 4(1): 3-11 (1985) |
| 1984 |
|---|
| 15 | | Israel Koren,
Melvin A. Breuer:
On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays.
IEEE Trans. Computers 33(1): 21-27 (1984) |
| 1983 |
|---|
| 14 | EE | Harold W. Carter,
Melvin A. Breuer:
Efficient Single-Layer Routing Along a Line of Points.
IEEE Trans. on CAD of Integrated Circuits and Systems 2(4): 259-266 (1983) |
| 1982 |
|---|
| 13 | | Miron Abramovici,
Melvin A. Breuer:
Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause Analysis.
IEEE Trans. Computers 31(12): 1165-1172 (1982) |
| 1981 |
|---|
| 12 | EE | Sarangan Krishna Kumar,
Melvin A. Breuer:
Probabilistic Aspects of Boolean Switching Functions via a New Transform.
J. ACM 28(3): 502-520 (1981) |
| 1980 |
|---|
| 11 | | Melvin A. Breuer,
Arthur D. Friedman:
Functional Level Primitives in Test Generation.
IEEE Trans. Computers 29(3): 223-235 (1980) |
| 10 | | Miron Abramovici,
Melvin A. Breuer:
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis.
IEEE Trans. Computers 29(6): 451-460 (1980) |
| 1979 |
|---|
| 9 | | Miron Abramovici,
Melvin A. Breuer:
On Redundancy and Fault Detection in Sequential Circuits.
IEEE Trans. Computers 28(11): 864-865 (1979) |
| 8 | | Prathima Agrawal,
Melvin A. Breuer:
Experiments with a Density Router for PC Cards.
IEEE Trans. Computers 28(3): 262-267 (1979) |
| 1976 |
|---|
| 7 | | Melvin A. Breuer,
Shih-Jeh Chang,
Stephen Y. H. Su:
Identification of Multiple Stuck-Type Faults in Combinational Networks.
IEEE Trans. Computers 25(1): 44-54 (1976) |
| 1970 |
|---|
| 6 | EE | Melvin A. Breuer:
Simplification of the Covering Problem with Application to Boolean Expressions.
J. ACM 17(1): 166-181 (1970) |
| 1969 |
|---|
| 5 | EE | Melvin A. Breuer:
Generation of optimal code for expressions via factorization.
Commun. ACM 12(6): 333-340 (1969) |
| 4 | | Melvin A. Breuer:
Combinatorial Equivalence of (0, 1) Circulant Matrices.
J. Comput. Syst. Sci. 3(1): 8-23 (1969) |
| 1968 |
|---|
| 3 | | Melvin A. Breuer:
Fault Detection in a Linear Cascade of Identical Machines
FOCS 1968: 235-243 |
| 1967 |
|---|
| 2 | | Melvin A. Breuer:
Adaptive Computers
Information and Control 11(4): 402-422 (1967) |
| 1964 |
|---|
| 1 | EE | Melvin A. Breuer:
Techniques for the simulation of computer logic.
Commun. ACM 7(7): 443-446 (1964) |
