| 2006 |
|---|
| 14 | EE | Debasis Mitra,
Subhasis Bhattacharjee,
Susmita Sur-Kolay,
Bhargab B. Bhattacharya,
Sujit T. Zachariah,
Sandip Kundu:
Test Pattern Generation for Power Supply Droop Faults.
VLSI Design 2006: 343-348 |
| 2005 |
|---|
| 13 | EE | Sandip Kundu,
Sujit T. Zachariah,
Yi-Shing Chang,
Chandra Tirumurti:
On modeling crosstalk faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1909-1915 (2005) |
| 2004 |
|---|
| 12 | EE | Susmita Sur-Kolay,
Parthasarathi Dasgupta,
Bhargab B. Bhattacharya,
Sujit T. Zachariah:
Physical Design Trends and Layout-Based Fault Modeling.
VLSI Design 2004: 6-8 |
| 11 | EE | Sujit T. Zachariah,
Sreejit Chakravarty:
Extraction of two-node bridges from large industrial circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 433-439 (2004) |
| 2003 |
|---|
| 10 | EE | Sujit T. Zachariah,
Yi-Shing Chang,
Sandip Kundu,
Chandra Tirumurti:
On Modeling Cross-Talk Faults.
DATE 2003: 10490-10495 |
| 9 | EE | Sujit T. Zachariah,
Sreejit Chakravarty:
Algorithm to extract two-node bridges.
IEEE Trans. VLSI Syst. 11(4): 741-744 (2003) |
| 2002 |
|---|
| 8 | EE | Sreejit Chakravarty,
Ankur Jain,
Nandakumar Radhakrishnan,
Eric W. Savage,
Sujit T. Zachariah:
Experimental Evaluation of Scan Tests for Bridges.
ITC 2002: 509-518 |
| 7 | EE | Sreejit Chakravarty,
Kambiz Komeyli,
Eric W. Savage,
Michael J. Carruthers,
Bret T. Stastny,
Sujit T. Zachariah:
Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms.
VTS 2002: 367-372 |
| 2001 |
|---|
| 6 | EE | Sujit T. Zachariah,
Sreejit Chakravarty:
A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits.
VLSI Design 2001: 333-338 |
| 5 | EE | Sandip Kundu,
Sujit T. Zachariah,
Sanjay Sengupta,
Rajesh Galivanche:
Test Challenges in Nanometer Technologies.
J. Electronic Testing 17(3-4): 209-218 (2001) |
| 2000 |
|---|
| 4 | EE | Sujit T. Zachariah,
Sreejit Chakravarty,
Carl D. Roth:
A novel algorithm to extract two-node bridges.
DAC 2000: 790-793 |
| 3 | | Sujit T. Zachariah,
Sreejit Chakravarty:
A scalable and efficient methodology to extract two node bridges from large industrial circuits.
ITC 2000: 750-759 |
| 2 | EE | Sreejit Chakravarty,
Sujit T. Zachariah:
STBM: a fast algorithm to simulate IDDQ tests forleakage faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 568-576 (2000) |
| 1999 |
|---|
| 1 | | Sujit T. Zachariah,
Sreejit Chakravarty:
A Comparative Study of Pseudo Stuck-At and Leakage Fault Model.
VLSI Design 1999: 91-94 |
