| 2008 |
|---|
| 6 | EE | Shianling Wu,
Laung-Terng Wang,
Zhigang Jiang,
Jiayong Song,
Boryau Sheu,
Xiaoqing Wen,
Michael Hsiao,
James Chien-Mo Li,
Jiun Lang Huang,
Ravi Apte:
On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.
DFT 2008: 143-151 |
| 5 | EE | Laung-Terng Wang,
Xiaoqing Wen,
Shianling Wu,
Zhigang Wang,
Zhigang Jiang,
Boryau Sheu,
Xinli Gu:
VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG.
IEEE Design & Test of Computers 25(2): 122-130 (2008) |
| 2005 |
|---|
| 4 | EE | Zhigang Jiang,
Sandeep K. Gupta:
Threshold testing: Covering bridging and other realistic faults.
Asian Test Symposium 2005: 390-397 |
| 2003 |
|---|
| 3 | EE | Zhigang Jiang,
Sandeep K. Gupta:
A Test Generation Approach for Systems-on-Chip that Use Intellectual Property Cores.
Asian Test Symposium 2003: 278-283 |
| 2 | EE | Md. Saffat Quasem,
Zhigang Jiang,
Sandeep K. Gupta:
Benefits of a SoC-Specific Test Methodology.
IEEE Design & Test of Computers 20(3): 68-77 (2003) |
| 2002 |
|---|
| 1 | EE | Zhigang Jiang,
Sandeep K. Gupta:
An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes.
ITC 2002: 824-833 |
