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2002 | ||
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2 | EE | B. Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina: Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture. ITC 2002: 574-583 |
1 | EE | Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich: Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. VTS 2002: 3-8 |
1 | Greg Aldrich | [1] |
2 | Mike Alexander | [2] |
3 | B. Bailey | [2] |
4 | Eric Fiene | [2] |
5 | Xijiang Lin | [1] |
6 | A. Metayer | [2] |
7 | Rajesh Raina | [1] [2] |
8 | B. Svrcek | [2] |
9 | Bruce Swanson | [1] |
10 | Nandu Tendolkar | [1] [2] |
11 | E. Wolf | [2] |