2009 |
48 | EE | Koji Yamazaki,
Toshiyuki Tsutsumi,
Hiroshi Takahashi,
Yoshinobu Higami,
Takashi Aikyo,
Yuzo Takamatsu,
Hiroyuki Yotsuyanagi,
Masaki Hashizume:
A Novel Approach for Improving the Quality of Open Fault Diagnosis.
VLSI Design 2009: 85-90 |
47 | EE | Hiroyuki Yotsuyanagi,
Masaki Hashizume,
Toshiyuki Tsutsumi,
Koji Yamazaki,
Takashi Aikyo,
Yoshinobu Higami,
Hiroshi Takahashi,
Yuzo Takamatsu:
Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC.
VLSI Design 2009: 91-96 |
2008 |
46 | EE | Yasuo Yamashita,
Hiroshi Takahashi,
Takao Terano:
The Development of the Financial Learning Tool through Business Game.
KES (2) 2008: 986-993 |
45 | EE | Yuzo Takamatsu,
Hiroshi Takahashi,
Yoshinobu Higami,
Takashi Aikyo,
Koji Yamazaki:
Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information.
IEICE Transactions 91-D(3): 675-682 (2008) |
44 | EE | Yoshinobu Higami,
Kewal K. Saluja,
Hiroshi Takahashi,
Shin-ya Kobayashi,
Yuzo Takamatsu:
Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools.
IEICE Transactions 91-D(3): 690-699 (2008) |
43 | EE | Hiroshi Takahashi,
Yoshinobu Higami,
Shuhei Kadoyama,
Yuzo Takamatsu,
Koji Yamazaki,
Takashi Aikyo,
Yasuo Sato:
Post-BIST Fault Diagnosis for Multiple Faults.
IEICE Transactions 91-D(3): 771-775 (2008) |
2007 |
42 | EE | Takashi Aikyo,
Hiroshi Takahashi,
Yoshinobu Higami,
Junichi Ootsu,
Kyohei Ono,
Yuzo Takamatsu:
Timing-Aware Diagnosis for Small Delay Defects.
DFT 2007: 223-234 |
41 | EE | Hiroshi Takahashi,
Yoshinobu Higami,
Toru Kikkawa,
Takashi Aikyo,
Yuzo Takamatsu,
Hiroyuki Yotsuyanagi,
Masaki Hashizume:
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines.
DFT 2007: 243-251 |
40 | EE | Hiroshi Takahashi,
Takao Terano:
Analyzing the Influence of Overconfident Investors on Financial Markets Through Agent-Based Model.
IDEAL 2007: 1042-1052 |
39 | EE | Satoru Takahashi,
Masakazu Takahashi,
Hiroshi Takahashi,
Kazuhiko Tsuda:
Analysis of the Relation Between Stock Price Returns and Headline News Using Text Categorization.
KES (2) 2007: 1339-1345 |
38 | EE | Yoshinobu Higami,
Kewal K. Saluja,
Hiroshi Takahashi,
Yuzo Takamatsu:
Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation.
VLSI Design 2007: 781-786 |
2006 |
37 | EE | Yoshinobu Higami,
Kewal K. Saluja,
Hiroshi Takahashi,
Shin-ya Kobayashi,
Yuzo Takamatsu:
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits.
ASP-DAC 2006: 659-664 |
36 | EE | Hiroshi Takahashi,
Shuhei Kadoyama,
Yoshinobu Higami,
Yuzo Takamatsu,
Koji Yamazaki,
Takashi Aikyo,
Yasuo Sato:
Effective Post-BIST Fault Diagnosis for Multiple Faults.
DFT 2006: 401-109 |
35 | EE | Satoru Takahashi,
Masakazu Takahashi,
Hiroshi Takahashi,
Kazuhiko Tsuda:
Analysis of Stock Price Return Using Textual Data and Numerical Data Through Text Mining.
KES (2) 2006: 310-316 |
34 | EE | Ikuo Matsuba,
Hiroshi Takahashi,
Shinya Wakasa:
Stochastically Equivalent Dynamical System Approach to Nonlinear Deterministic Prediction.
I. J. Bifurcation and Chaos 16(9): 2721-2728 (2006) |
2005 |
33 | EE | T. Seiyama,
Hiroshi Takahashi,
Yoshinobu Higami,
Kazuo Yamazaki,
Yuzo Takamatsu:
On the fault diagnosis in the presence of unknown fault models using pass/fail information.
ISCAS (3) 2005: 2987-2990 |
32 | EE | Satoru Takahashi,
Masakazu Takahashi,
Hiroshi Takahashi,
Kazuhiko Tsuda:
Learning Value-Added Information of Asset Management from Analyst Reports Through Text Mining.
KES (4) 2005: 785-791 |
31 | EE | Hiroshi Takahashi,
Keith J. Keller,
Kim T. Le,
Kewal K. Saluja,
Yuzo Takamatsu:
A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 252-263 (2005) |
30 | EE | Akihiko Hirata,
Hiroyoshi Togo,
Naofumi Shimizu,
Hiroshi Takahashi,
Katsunari Okamoto,
Tadao Nagatsuma:
Low-Phase Noise Photonic Millimeter-Wave Generator Using an AWG Integrated with a 3-dB Combiner.
IEICE Transactions 88-C(7): 1458-1464 (2005) |
2004 |
29 | EE | Hiroshi Takahashi,
Yukihiro Yamamoto,
Yoshinobu Higami,
Yuzo Takamatsu:
Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set.
Asian Test Symposium 2004: 216-221 |
28 | EE | Yuichi Sato,
Hiroshi Takahashi,
Yoshinobu Higami,
Yuzo Takamatsu:
Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests.
Asian Test Symposium 2004: 222-227 |
27 | EE | Satoru Takahashi,
Hiroshi Takahashi,
Kazuhiko Tsuda:
An Efficient Learning System for Knowledge of Asset Management.
KES 2004: 494-500 |
2003 |
26 | EE | Hiroshi Takahashi,
Yasunori Tsugaoka,
Hidekazu Ayano,
Yuzo Takamatsu:
BIST Based Fault Diagnosis Using Ambiguous Test Set.
DFT 2003: 89-96 |
25 | | Ikuo Matsuba,
Hiroshi Takahashi,
Shinya Wakasa:
Stochastically Equivalent Dynamical System Approach To Nonlinear Deterministic Prediction.
HIS 2003: 409-418 |
24 | EE | Hiroshi Takahashi,
Takao Terano:
Agent-Based Approach to Investors' Behavior and Asset Price Fluctuation in Financial Markets.
J. Artificial Societies and Social Simulation 6(3): (2003) |
2002 |
23 | EE | Keith J. Keller,
Hiroshi Takahashi,
Kim T. Le,
Kewal K. Saluja,
Yuzo Takamatsu:
Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints.
Asian Test Symposium 2002: 242-247 |
22 | EE | Jiang Brandon Liu,
Andreas G. Veneris,
Hiroshi Takahashi:
Incremental Diagnosis of Multiple Open-Interconnects.
ITC 2002: 1085-1092 |
21 | EE | Hiroshi Takahashi,
Kewal K. Saluja,
Yuzo Takamatsu:
An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets.
PRDC 2002: 275-282 |
20 | EE | Hiroshi Takahashi,
Kwame Osei Boateng,
Kewal K. Saluja,
Yuzo Takamatsu:
On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 362-368 (2002) |
2001 |
19 | EE | Hiroshi Takahashi,
Marong Phadoongsidhi,
Yoshinobu Higami,
Kewal K. Saluja,
Yuzo Takamatsu:
Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits.
Asian Test Symposium 2001: 63- |
18 | | Keith J. Keller,
Hiroshi Takahashi,
Kewal K. Saluja,
Yuzo Takamatsu:
On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits.
ITC 2001: 568-577 |
17 | EE | Thomas Clouqueur,
Ozen Ercevik,
Kewal K. Saluja,
Hiroshi Takahashi:
Efficient Signature-Based Fault Diagnosis Using Variable Size Windows.
VLSI Design 2001: 391-396 |
2000 |
16 | EE | Kwame Osei Boateng,
Hiroshi Takahashi,
Yuzo Takamatsu:
General BIST-Amenable Method of Test Generation for Iterative Logic Arrays.
VTS 2000: 171-178 |
15 | EE | Satoshi Koizumi,
Masayuki Matsushita,
Yasufumi Takama,
Hiroshi Takahashi,
Kaoru Hirota:
Temporal-Hierarchical Emergency-Degree Inference System for Running Vehicles Using Image and Navigation Data.
JACIII 4(1): 76-87 (2000) |
1999 |
14 | EE | Teruhiko Yamada,
Toshinori Kotake,
Hiroshi Takahashi,
Koji Yamazaki:
Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset.
Asian Test Symposium 1999: 269-274 |
13 | EE | Hiroshi Takahashi,
Kwame Osei Boateng,
Yuzo Takamatsu,
Nobuhiro Yanagida:
Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators.
Asian Test Symposium 1999: 341-346 |
12 | EE | Hiroshi Takahashi,
Kwame Osei Boateng,
Yuzo Takamatsu:
A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations.
VTS 1999: 64-69 |
11 | EE | Hiroshi Takahashi,
Kouichi Kuroda:
Study on Intelligent Vehicle Control Considering Driver Perception of Driving Environment.
JACIII 3(1): 42-49 (1999) |
1998 |
10 | EE | Hiroshi Takahashi,
Kwame Osei Boateng,
Yuzo Takamatsu:
Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation.
Asian Test Symposium 1998: 108-112 |
9 | EE | Nobuhiro Yanagida,
Hiroshi Takahashi,
Yuzo Takamatsu:
Electron Beam Tester Aided Fault Diagnosis for Logic Circuits Based on Sensitized Paths.
Asian Test Symposium 1998: 237- |
1997 |
8 | EE | Hiroshi Takahashi,
Kwame Osei Boateng,
Yuzo Takamatsu,
Toshiyuki Matsunaga:
A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits.
Asian Test Symposium 1997: 320-325 |
7 | EE | Kwame Osei Boateng,
Hiroshi Takahashi,
Yuzo Takamatsu:
Design of C-Testable Multipliers Based on the Modified Booth Algorithm.
Asian Test Symposium 1997: 42-47 |
6 | EE | Hiroshi Takahashi:
Vehicle Control Based on Fuzzy Evaluation Knowledge Obtained by Coefficients of the ARMA Model.
JACIII 1(1): 8-9 (1997) |
5 | EE | Hiroshi Takahashi,
Takashi Watanabe,
Toshiyuki Matsunaga,
Yuzo Takamatsu:
Tests for small gate delay faults in combinational circuits and a test generation method.
Systems and Computers in Japan 28(6): 68-76 (1997) |
1996 |
4 | | Nobuhiro Yanagida,
Hiroshi Takahashi,
Yuzo Takamatsu:
Multiple Fault Diagnosis in Sequential Circuits Using Sensitizing Sequence Pairs.
FTCS 1996: 86-95 |
1995 |
3 | EE | Hiroshi Takahashi,
Takashi Watanabe,
Yuzo Takamatsu:
Generation of tenacious tests for small gate delay faults in combinational circuits.
Asian Test Symposium 1995: 332-338 |
2 | EE | Hiroshi Takahashi,
Nobuhiro Yanagida,
Yuzo Takamatsu:
Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing.
Asian Test Symposium 1995: 58-64 |
1 | EE | Nobuhiro Yanagida,
Hiroshi Takahashi,
Yuzo Takamatsu:
Multiple Fault Diagnosis by Sensitizing Input Pairs.
IEEE Design & Test of Computers 12(3): 44-52 (1995) |