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Marcelino B. Santos

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2008
34EEJorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits. DDECS 2008: 34-37
2007
33 Jorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits. DDECS 2007: 295-300
32EEJorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits. IOLTS 2007: 167-172
31EEJorge Semião, J. Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Enhancing the Tolerance to Power-Supply Instability in Digital Circuits. ISVLSI 2007: 207-212
2006
30 José M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João C. Teixeira: Probabilistic Testability Analysis and DFT Methods at RTL. DDECS 2006: 216-217
29 F. Guerreiro, Jorge Semião, A. Pierce, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Functional-Oriented BIST of Sequential Circuits Aiming at Dynamic Faults Coverage. DDECS 2006: 279-284
2005
28EEM. Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test. IOLTS 2005: 281-286
27EED. Barros Júnior, M. Rodríguez-Irago, Marcelino B. Santos, Isabel C. Teixeira, Fabian Vargas, João Paulo Teixeira: Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip. J. Electronic Testing 21(4): 349-363 (2005)
2004
26EEJosé M. Fernandes, Marcelino B. Santos, Arlindo L. Oliveira, João C. Teixeira: A Probabilistic Method for the Computation of Testability of RTL Constructs. DATE 2004: 176-181
25EEA. Parreira, João Paulo Teixeira, Marcelino B. Santos: FPGAs BIST Evaluation. FPL 2004: 333-343
24EEDaniel Barros Jr., Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Modeling and Simulation of Time Domain Faults in Digital Systems. IOLTS 2004: 5-10
23 A. Parreira, João Paulo Teixeira, Marcelino B. Santos: Built-In Self-Test Quality Assessment Using Hardware Fault Emulation In FPGAs. Computers and Artificial Intelligence 23(5): (2004)
22EEMarcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, L. Balado, Joan Figueras: On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level. J. Electronic Testing 20(4): 345-355 (2004)
2003
21EEMarcelino B. Santos, José M. Fernandes, Isabel C. Teixeira, João Paulo Teixeira: RTL Test Pattern Generation for High Quality Loosely Deterministic BIST. DATE 2003: 10994-10999
20EEA. Parreira, João Paulo Teixeira, A. Pantelimon, Marcelino B. Santos, José T. de Sousa: Fault Simulation Using Partially Reconfigurable Hardware. FPL 2003: 839-848
19EEFernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems. IOLTS 2003: 164-165
2002
18EEFernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling. DFT 2002: 216-224
17EEMarcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras: RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. ITC 2002: 814-823
16EEMarcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira: RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage. J. Electronic Testing 18(2): 179-187 (2002)
15EEFernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System. J. Electronic Testing 18(3): 285-294 (2002)
2001
14EEFernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro. IOLTW 2001: 197-201
13 Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level. ITC 2001: 377-385
12EEMarcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira: RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems. J. Electronic Testing 17(3-4): 311-319 (2001)
2000
11EEOctávio Páscoa Dias, Jorge Semião, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Quality of Electronic Design: From Architectural Level to Test Coverage. ISQED 2000: 197-
1999
10EEMarcelino B. Santos, João Paulo Teixeira: Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL. DATE 1999: 549-
9EEMarcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira: Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique. VTS 1999: 326-332
1998
8EEFernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Defect-oriented test quality assessment using fault sampling and simulation. ITC 1998: 35-42
1996
7 F. Celeiro, L. Dias, J. Ferreira, Marcelino B. Santos, João Paulo Teixeira: Defect-Oriented IC Test and Diagnosis Using VHDL Fault Simulation. ITC 1996: 620-628
1995
6EEMarcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira: Test preparation for high coverage of physical defects in CMOS digital ICs. VTS 1995: 330-337
1994
5 Antonio Casimiro, F. Conçalves, João Paulo Teixeira, Marcelino B. Santos: On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits. DFT 1994: 263-270
4 M. Calha, Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira: Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs. ITC 1994: 720-728
1993
3 Antonio Casimiro, M. Simões, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs. DFT 1993: 109-116
2 P. Nicolau, J. Barbosa, M. Saraiva, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Realistic Fault Analysis of CMOS Analog Building Blocks. DFT 1993: 311-318
1992
1 M. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira: Physical DFT for High Coverage of Realistic Faults. ITC 1992: 642-651

Coauthor Index

1L. Balado [22]
2J. Barbosa [2]
3Daniel Barros Jr. [24]
4M. Calha [4]
5Antonio Casimiro [3] [5]
6P. Casimiro [1]
7F. Celeiro [7]
8F. Conçalves [5]
9L. Dias [7]
10Octávio Páscoa Dias [11]
11José M. Fernandes [21] [26] [30]
12J. Ferreira [7]
13Joan Figueras [17] [22]
14J. Freijedo [31] [32] [33]
15Fernando M. Gonçalves [1] [4] [8] [9] [12] [13] [14] [15] [16] [18] [19]
16F. Guerreiro [29]
17D. Barros Júnior [27]
18Salvador Manich [17] [22]
19P. Nicolau [2]
20Arlindo L. Oliveira [26] [30]
21A. Pantelimon [20]
22A. Parreira [20] [23] [25]
23A. Pierce [29]
24Juan J. Rodríguez-Andina [28] [31] [32] [33] [34]
25M. Rodríguez-Irago [27] [28]
26Rosa Rodríguez-Montañés [17]
27M. Saraiva [1] [2]
28Jorge Semião [11] [29] [31] [32] [33] [34]
29M. Simões [3] [6]
30José T. de Sousa [1] [20]
31Isabel C. Teixeira [1] [2] [3] [4] [6] [8] [9] [11] [12] [13] [14] [15] [16] [17] [18] [19] [21] [22] [24] [27] [28] [29] [31] [32] [33] [34]
32João C. Teixeira [26] [30]
33João Paulo Teixeira [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [27] [28] [29] [31] [32] [33] [34]
34Fabian Vargas [24] [27] [28] [31] [32] [33] [34]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)