| 2008 |
|---|
| 93 | EE | Melanie Elm,
Hans-Joachim Wunderlich,
Michael E. Imhof,
Christian G. Zoellin,
Jens Leenstra,
Nicolas Mäding:
Scan chain clustering for test power reduction.
DAC 2008: 828-833 |
| 92 | EE | Melanie Elm,
Hans-Joachim Wunderlich:
Scan Chain Organization for Embedded Diagnosis.
DATE 2008: 468-473 |
| 91 | EE | Michael A. Kochte,
Christian G. Zoellin,
Michael E. Imhof,
Hans-Joachim Wunderlich:
Test Set Stripping Limiting the Maximum Number of Specified Bits.
DELTA 2008: 581-586 |
| 90 | EE | Uranmandakh Amgalan,
Christian Hachmann,
Sybille Hellebrand,
Hans-Joachim Wunderlich:
Signature Rollback - A Technique for Testing Robust Circuits.
VTS 2008: 125-130 |
| 2007 |
|---|
| 89 | EE | Valentin Gherman,
Hans-Joachim Wunderlich,
R. D. Mascarenhas,
Jürgen Schlöffel,
Michael Garbers:
Synthesis of irregular combinational functions with large don't care sets.
ACM Great Lakes Symposium on VLSI 2007: 287-292 |
| 88 | EE | Michael E. Imhof,
Christian G. Zoellin,
Hans-Joachim Wunderlich,
Nicolas Mäding,
Jens Leenstra:
Scan Test Planning for Power Reduction.
DAC 2007: 521-526 |
| 87 | | Philipp Öhler,
Sybille Hellebrand,
Hans-Joachim Wunderlich:
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.
DDECS 2007: 185-190 |
| 86 | EE | Sybille Hellebrand,
Christian G. Zoellin,
Hans-Joachim Wunderlich,
Stefan Ludwig,
Torsten Coym,
Bernd Straube:
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction.
DFT 2007: 50-58 |
| 85 | EE | Stefan Holst,
Hans-Joachim Wunderlich:
Adaptive Debug and Diagnosis without Fault Dictionaries.
European Test Symposium 2007: 7-12 |
| 84 | EE | Philipp Öhler,
Sybille Hellebrand,
Hans-Joachim Wunderlich:
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy.
European Test Symposium 2007: 91-96 |
| 2006 |
|---|
| 83 | EE | Jun Zhou,
Hans-Joachim Wunderlich:
Software-based self-test of processors under power constraints.
DATE 2006: 430-435 |
| 82 | EE | Talal Arnaout,
Gunter Bartsch,
Hans-Joachim Wunderlich:
Some Common Aspects of Design Validation, Debug and Diagnosis.
DELTA 2006: 3-10 |
| 81 | EE | Valentin Gherman,
Hans-Joachim Wunderlich,
Jürgen Schlöffel,
Michael Garbers:
Deterministic Logic BIST for Transition Fault Testing.
European Test Symposium 2006: 123-130 |
| 80 | EE | Nabil Badereddine,
Patrick Girard,
Serge Pravossoudovitch,
Christian Landrault,
Arnaud Virazel,
Hans-Joachim Wunderlich:
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.
VLSI-SoC 2006: 403-408 |
| 79 | EE | Yuyi Tang,
Hans-Joachim Wunderlich,
Piet Engelke,
Ilia Polian,
Bernd Becker,
Jürgen Schlöffel,
Friedrich Hapke,
Michael Wittke:
X-masking during logic BIST and its impact on defect coverage.
IEEE Trans. VLSI Syst. 14(2): 193-202 (2006) |
| 78 | EE | Bernd Becker,
Ilia Polian,
Sybille Hellebrand,
Bernd Straube,
Hans-Joachim Wunderlich:
DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems).
it - Information Technology 48(5): 304- (2006) |
| 2005 |
|---|
| 77 | | Olivier Héron,
Talal Arnaout,
Hans-Joachim Wunderlich:
On the Reliability Evaluation of SRAM-Based FPGA Designs.
FPL 2005: 403-408 |
| 76 | | Jun Zhou,
Hans-Joachim Wunderlich:
Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschränkung.
GI Jahrestagung (1) 2005: 441 |
| 75 | EE | Pattara Kiatisevi,
Luis Leonardo Azuara-Gomez,
Rainer Dorsch,
Hans-Joachim Wunderlich:
Development of an audio player as system-on-a-chip using an open source platform.
ISCAS (3) 2005: 2935-2938 |
| 74 | EE | Abdul Wahid Hakmi,
Hans-Joachim Wunderlich,
Valentin Gherman,
Michael Garbers,
Jürgen Schlöffel:
Implementing a Scheme for External Deterministic Self-Test.
VTS 2005: 101-106 |
| 2004 |
|---|
| 73 | | Talal Arnaout,
Peter Göhner,
Hans-Joachim Wunderlich,
Eduard Zimmer:
Reliability Considerations forMechatronic Systems on the Basis of a State Model.
ARCS Workshops 2004: 106-112 |
| 72 | EE | Harald P. E. Vranken,
Ferry Syafei Sapei,
Hans-Joachim Wunderlich:
Impact of Test Point Insertion on Silicon Area and Timing during Layout.
DATE 2004: 810-815 |
| 71 | EE | Marie-Lise Flottes,
Yves Bertrand,
L. Balado,
E. Lupon,
Anton Biasizzo,
Franc Novak,
Stefano Di Carlo,
Paolo Prinetto,
N. Pricopi,
Hans-Joachim Wunderlich:
Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ.
DELTA 2004: 135-139 |
| 70 | EE | Yuyi Tang,
Hans-Joachim Wunderlich,
Harald P. E. Vranken,
Friedrich Hapke,
Michael Wittke,
Piet Engelke,
Ilia Polian,
Bernd Becker:
X-Masking During Logic BIST and Its Impact on Defect Coverage.
ITC 2004: 442-451 |
| 69 | EE | Valentin Gherman,
Hans-Joachim Wunderlich,
Harald P. E. Vranken,
Friedrich Hapke,
Michael Wittke,
Michael Garbers:
Efficient Pattern Mapping for Deterministic Logic BIST.
ITC 2004: 48-56 |
| 68 | | Hans-Joachim Wunderlich,
Sandeep K. Shukla:
Panel Summaries.
IEEE Design & Test of Computers 21(1): 65-66 (2004) |
| 2003 |
|---|
| 67 | EE | Yves Bertrand,
Marie-Lise Flottes,
L. Balado,
Joan Figueras,
Anton Biasizzo,
Franc Novak,
Stefano Di Carlo,
Paolo Prinetto,
N. Pricopi,
Hans-Joachim Wunderlich,
J.-P. Van der Heyden:
Test Engineering Education in Europe: the EuNICE-Test Project.
MSE 2003: 85-86 |
| 66 | EE | Shishpal Rawat,
Hans-Joachim Wunderlich:
Introduction.
ACM Trans. Design Autom. Electr. Syst. 8(4): 397-398 (2003) |
| 2002 |
|---|
| 65 | EE | Rainer Dorsch,
Ramón Huerta Rivera,
Hans-Joachim Wunderlich,
Martin Fischer:
Adapting an SoC to ATE Concurrent Test Capabilities.
ITC 2002: 1169-1175 |
| 64 | EE | Patrick Girard,
Christian Landrault,
Serge Pravossoudovitch,
Arnaud Virazel,
Hans-Joachim Wunderlich:
High Defect Coverage with Low-Power Test Sequences in a BIST Environment.
IEEE Design & Test of Computers 19(5): 44-52 (2002) |
| 63 | EE | Sybille Hellebrand,
Hans-Joachim Wunderlich,
Alexander A. Ivaniuk,
Yuri V. Klimets,
Vyacheslav N. Yarmolik:
Efficient Online and Offline Testing of Embedded DRAMs.
IEEE Trans. Computers 51(7): 801-809 (2002) |
| 62 | EE | Huaguo Liang,
Sybille Hellebrand,
Hans-Joachim Wunderlich:
A Mixed-Mode BIST Scheme Based on Folding Compression.
J. Comput. Sci. Technol. 17(2): 203-212 (2002) |
| 61 | EE | Huaguo Liang,
Sybille Hellebrand,
Hans-Joachim Wunderlich:
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.
J. Electronic Testing 18(2): 159-170 (2002) |
| 60 | EE | Rainer Dorsch,
Hans-Joachim Wunderlich:
Reusing Scan Chains for Test Pattern Decompression.
J. Electronic Testing 18(2): 231-240 (2002) |
| 2001 |
|---|
| 59 | EE | Silvia Chiusano,
Stefano Di Carlo,
Paolo Prinetto,
Hans-Joachim Wunderlich:
On applying the set covering model to reseeding.
DATE 2001: 156-161 |
| 58 | EE | Rainer Dorsch,
Hans-Joachim Wunderlich:
Using mission logic for embedded testing.
DATE 2001: 805 |
| 57 | EE | A. Irion,
Gundolf Kiefer,
Harald P. E. Vranken,
Hans-Joachim Wunderlich:
Circuit partitioning for efficient logic BIST synthesis.
DATE 2001: 86-91 |
| 56 | | Michael Kessler,
Gundolf Kiefer,
Jens Leenstra,
Knut Schünemann,
Thomas Schwarz,
Hans-Joachim Wunderlich:
Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability.
ITC 2001: 461-469 |
| 55 | | Rainer Dorsch,
Hans-Joachim Wunderlich:
Tailoring ATPG for embedded testing.
ITC 2001: 530-537 |
| 54 | | Huaguo Liang,
Sybille Hellebrand,
Hans-Joachim Wunderlich:
Two-dimensional test data compression for scan-based deterministic BIST.
ITC 2001: 894-902 |
| 53 | EE | Patrick Girard,
Loïs Guiller,
Christian Landrault,
Serge Pravossoudovitch,
Hans-Joachim Wunderlich:
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator.
VTS 2001: 306-311 |
| 52 | EE | Sybille Hellebrand,
Huaguo Liang,
Hans-Joachim Wunderlich:
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.
J. Electronic Testing 17(3-4): 341-349 (2001) |
| 51 | EE | Gundolf Kiefer,
Harald P. E. Vranken,
Erik Jan Marinissen,
Hans-Joachim Wunderlich:
Application of Deterministic Logic BIST on Industrial Circuits.
J. Electronic Testing 17(3-4): 351-362 (2001) |
| 2000 |
|---|
| 50 | EE | Silvia Cataldo,
Silvia Chiusano,
Paolo Prinetto,
Hans-Joachim Wunderlich:
Optimal Hardware Pattern Generation for Functional BIST.
DATE 2000: 292-297 |
| 49 | | Gundolf Kiefer,
Hans-Joachim Wunderlich,
Harald P. E. Vranken,
Erik Jan Marinissen:
Application of deterministic logic BIST on industrial circuits.
ITC 2000: 105-114 |
| 48 | | Silvia Chiusano,
Paolo Prinetto,
Hans-Joachim Wunderlich:
Non-intrusive BIST for systems-on-a-chip.
ITC 2000: 644-651 |
| 47 | | Sybille Hellebrand,
Hans-Joachim Wunderlich,
Huaguo Liang:
A mixed mode BIST scheme based on reseeding of folding counters.
ITC 2000: 778-784 |
| 46 | EE | Gundolf Kiefer,
Hans-Joachim Wunderlich:
Deterministic BIST with Partial Scan.
J. Electronic Testing 16(3): 169-177 (2000) |
| 45 | EE | Stefan Gerstendörfer,
Hans-Joachim Wunderlich:
Minimized Power Consumption for Scan-Based BIST.
J. Electronic Testing 16(3): 203-212 (2000) |
| 1999 |
|---|
| 44 | EE | Sybille Hellebrand,
Hans-Joachim Wunderlich,
Vyacheslav N. Yarmolik:
Symmetric Transparent BIST for RAMs.
DATE 1999: 702-707 |
| 43 | EE | Vyacheslav N. Yarmolik,
I. V. Bykov,
Sybille Hellebrand,
Hans-Joachim Wunderlich:
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms.
EDCC 1999: 339-350 |
| 42 | | Stefan Gerstendörfer,
Hans-Joachim Wunderlich:
Minimized power consumption for scan-based BIST.
ITC 1999: 77-84 |
| 41 | EE | Sybille Hellebrand,
Hans-Joachim Wunderlich,
Alexander A. Ivaniuk,
Yuri V. Klimets,
Vyacheslav N. Yarmolik:
Error Detecting Refreshment for Embedded DRAMs.
VTS 1999: 384-390 |
| 40 | EE | Gundolf Kiefer,
Hans-Joachim Wunderlich:
Deterministic BIST with Multiple Scan Chains.
J. Electronic Testing 14(1-2): 85-93 (1999) |
| 1998 |
|---|
| 39 | EE | Madhavi Karkala,
Nur A. Touba,
Hans-Joachim Wunderlich:
Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST.
Asian Test Symposium 1998: 492-499 |
| 38 | EE | Vyacheslav N. Yarmolik,
Sybille Hellebrand,
Hans-Joachim Wunderlich:
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs.
DATE 1998: 173-179 |
| 37 | EE | Gundolf Kiefer,
Hans-Joachim Wunderlich:
Deterministic BIST with multiple scan chains.
ITC 1998: 1057-1064 |
| 36 | EE | Rainer Dorsch,
Hans-Joachim Wunderlich:
Accumulator based deterministic BIST.
ITC 1998: 412-421 |
| 35 | EE | Andre Hertwig,
Sybille Hellebrand,
Hans-Joachim Wunderlich:
Fast Self-Recovering Controllers.
VTS 1998: 296-302 |
| 34 | EE | Sybille Hellebrand,
Hans-Joachim Wunderlich,
Andre Hertwig:
Synthesizing Fast, Online-Testable Control Units.
IEEE Design & Test of Computers 15(4): 36-41 (1998) |
| 33 | EE | Albrecht P. Stroele,
Hans-Joachim Wunderlich:
Hardware-optimal test register insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 531-539 (1998) |
| 32 | EE | Hans-Joachim Wunderlich:
BIST for systems-on-a-chip.
Integration 26(1-2): 55-78 (1998) |
| 31 | EE | Sybille Hellebrand,
Hans-Joachim Wunderlich,
Andre Hertwig:
Mixed-Mode BIST Using Embedded Processors.
J. Electronic Testing 12(1-2): 127-138 (1998) |
| 1997 |
|---|
| 30 | EE | Andre Hertwig,
Hans-Joachim Wunderlich:
Fast controllers for data dominated applications.
ED&TC 1997: 84-89 |
| 29 | | Gundolf Kiefer,
Hans-Joachim Wunderlich:
Using BIST Control for Pattern Generation.
ITC 1997: 347-355 |
| 28 | EE | Vishwani D. Agrawal,
Robert C. Aitken,
J. Braden,
Joan Figueras,
S. Kumar,
Hans-Joachim Wunderlich,
Yervant Zorian:
Power Dissipation During Testing: Should We Worry About it?
VTS 1997: 456-457 |
| 27 | EE | K.-T. Cheng,
Kewal K. Saluja,
Hans-Joachim Wunderlich:
Guest Editorial.
J. Electronic Testing 11(1): 7-8 (1997) |
| 1996 |
|---|
| 26 | EE | Hans-Joachim Wunderlich,
Gundolf Kiefer:
Bit-flipping BIST.
ICCAD 1996: 337-343 |
| 25 | | Sybille Hellebrand,
Hans-Joachim Wunderlich,
Andre Hertwig:
Mixed-Mode BIST Using Embedded Processors.
ITC 1996: 195-204 |
| 1995 |
|---|
| 24 | EE | Sybille Hellebrand,
Birgit Reeb,
Steffen Tarnick,
Hans-Joachim Wunderlich:
Pattern generation for a deterministic BIST scheme.
ICCAD 1995: 88-94 |
| 23 | EE | Albrecht P. Stroele,
Hans-Joachim Wunderlich:
Test register insertion with minimum hardware cost.
ICCAD 1995: 95-101 |
| 1994 |
|---|
| 22 | | Sybille Hellebrand,
Hans-Joachim Wunderlich:
Synthesis of Self-Testable Controllers.
EDAC-ETC-EUROASIC 1994: 580-585 |
| 21 | EE | Sybille Hellebrand,
Hans-Joachim Wunderlich:
An efficient procedure for the synthesis of fast self-testable controller structures.
ICCAD 1994: 110-116 |
| 20 | | Olaf Stern,
Hans-Joachim Wunderlich:
Simulation Results of an Efficient Defect-Analysis Procedure.
ITC 1994: 729-738 |
| 19 | | Albrecht P. Stroele,
Hans-Joachim Wunderlich:
Configuring Flip-Flops to BIST Registers.
ITC 1994: 939-948 |
| 1992 |
|---|
| 18 | EE | Hans-Joachim Wunderlich,
Sybille Hellebrand:
The pseudoexhaustive test of sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(1): 26-33 (1992) |
| 17 | EE | Bernhard Eschermann,
Hans-Joachim Wunderlich:
Optimized synthesis techniques for testable sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(3): 301-312 (1992) |
| 16 | | Hans-Joachim Wunderlich,
Michael H. Schulz:
Prüfgerechter Entwurf und Test hochintegrierter Schaltungen.
Informatik Spektrum 15(1): 23-32 (1992) |
| 1991 |
|---|
| 15 | EE | Bernhard Eschermann,
Hans-Joachim Wunderlich:
A Unified Approach for the Synthesis of Self-Testable Finite State Machines.
DAC 1991: 372-377 |
| 14 | | Albrecht P. Stroele,
Hans-Joachim Wunderlich:
Signature Analysis and Test Scheduling for Self-Testable Circuits.
FTCS 1991: 96-103 |
| 13 | | Bernhard Eschermann,
Hans-Joachim Wunderlich:
Emulation of Scan Paths in Sequential Circuit Synthesis.
Fault-Tolerant Computing Systems 1991: 136-147 |
| 12 | | Thomas Kropf,
Hans-Joachim Wunderlich:
A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic.
ITC 1991: 57-66 |
| 1990 |
|---|
| 11 | EE | Sybille Hellebrand,
Hans-Joachim Wunderlich:
Tools and devices supporting the pseudo-exhaustive test.
EURO-DAC 1990: 13-17 |
| 10 | EE | Peter C. Maxwell,
Hans-Joachim Wunderlich:
The effectiveness of different test sets for PLAs.
EURO-DAC 1990: 628-632 |
| 9 | EE | Hans-Joachim Wunderlich:
Multiple distributions for biased random test patterns.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(6): 584-593 (1990) |
| 8 | EE | Arno Kunzmann,
Hans-Joachim Wunderlich:
An analytical approach to the partial scan problem.
J. Electronic Testing 1(2): 163-174 (1990) |
| 1989 |
|---|
| 7 | | Sybille Hellebrand,
Hans-Joachim Wunderlich:
The Pseudo-Exhaustive Test of Sequential Circuits.
ITC 1989: 19-27 |
| 1988 |
|---|
| 6 | | Sybille Hellebrand,
Hans-Joachim Wunderlich:
Automatisierung des Entwurfs vollständig testbarer Schaltungen.
GI Jahrestagung (2) 1988: 145-159 |
| 5 | | Hans-Joachim Wunderlich:
Multiple Distributions for Biased Random Test Patterns.
ITC 1988: 236-244 |
| 1987 |
|---|
| 4 | | Hans-Joachim Wunderlich:
Probabilistische Verfahren für den Test hochintegrierter Schaltungen
Springer 1987 |
| 3 | EE | Hans-Joachim Wunderlich:
On Computing Optimized Input Probabilities for Random Tests.
DAC 1987: 392-398 |
| 1986 |
|---|
| 2 | EE | Hans-Joachim Wunderlich,
Wolfgang Rosenstiel:
On fault modeling for dynamic MOS circuits.
DAC 1986: 540-546 |
| 1985 |
|---|
| 1 | EE | Hans-Joachim Wunderlich:
PROTEST: a tool for probabilistic testability analysis.
DAC 1985: 204-211 |
