2008 |
22 | EE | Ying-Yen Chen,
Jing-Jia Liou:
Diagnosis Framework for Locating Failed Segments of Path Delay Faults.
IEEE Trans. VLSI Syst. 16(6): 755-765 (2008) |
2007 |
21 | EE | Ying-Yen Chen,
Jing-Jia Liou:
Extraction of Statistical Timing Profiles Using Test Data.
DAC 2007: 509-514 |
20 | EE | Jyun-Wei Chen,
Ying-Yen Chen,
Jing-Jia Liou:
Handling Pattern-Dependent Delay Faults in Diagnosis.
VTS 2007: 151-157 |
2006 |
19 | EE | Ying-Yen Chen,
Jing-Jia Liou:
Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method.
DFT 2006: 428-438 |
18 | EE | Shun-Yen Lu,
Pei-Ying Hsieh,
Jing-Jia Liou:
Exploring linear structures of critical path delay faults to reduce test efforts.
ICCAD 2006: 100-106 |
2005 |
17 | EE | Chun-Chieh Wang,
Jing-Jia Liou,
Yen-Lin Peng,
Chih-Tsun Huang,
Cheng-Wen Wu:
A BIST Scheme for FPGA Interconnect Delay Faults.
VTS 2005: 201-206 |
2004 |
16 | EE | Yen-Lin Peng,
Jing-Jia Liou,
Chih-Tsun Huang,
Cheng-Wen Wu:
An Application-Independent Delay Testing Methodology for Island-Style FPGA.
DFT 2004: 478-486 |
15 | EE | Li-C. Wang,
Jing-Jia Liou,
Kwang-Ting Cheng:
Critical path selection for delay fault testing based upon a statistical timing model.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(11): 1550-1565 (2004) |
2003 |
14 | EE | Angela Krstic,
Li-C. Wang,
Kwang-Ting Cheng,
Jing-Jia Liou,
T. M. Mak:
Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models.
DAC 2003: 668-673 |
13 | EE | Angela Krstic,
Li-C. Wang,
Kwang-Ting Cheng,
Jing-Jia Liou,
Magdy S. Abadir:
Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step.
DATE 2003: 10328-10335 |
12 | EE | Angela Krstic,
Jing-Jia Liou,
Kwang-Ting Cheng,
Li-C. Wang:
On Structural vs. Functional Testing for Delay Faults.
ISQED 2003: 438-441 |
11 | EE | Angela Krstic,
Li-C. Wang,
Kwang-Ting Cheng,
Jing-Jia Liou:
Diagnosis of Delay Defects Using Statistical Timing Models.
VTS 2003: 339-344 |
10 | EE | Jing-Jia Liou,
Angela Krstic,
Yi-Min Jiang,
Kwang-Ting Cheng:
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 756-769 (2003) |
2002 |
9 | EE | Jing-Jia Liou,
Li-C. Wang,
Kwang-Ting Cheng,
Jennifer Dworak,
M. Ray Mercer,
Rohit Kapur,
Thomas W. Williams:
Enhancing test efficiency for delay fault testing using multiple-clocked schemes.
DAC 2002: 371-374 |
8 | EE | Jing-Jia Liou,
Angela Krstic,
Li-C. Wang,
Kwang-Ting Cheng:
False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation.
DAC 2002: 566-569 |
7 | EE | Jing-Jia Liou,
Li-C. Wang,
Kwang-Ting Cheng:
On theoretical and practical considerations of path selection for delay fault testing.
ICCAD 2002: 94-100 |
6 | EE | Jing-Jia Liou,
Li-C. Wang,
Kwang-Ting Cheng,
Jennifer Dworak,
M. Ray Mercer,
Rohit Kapur,
Thomas W. Williams:
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme.
ITC 2002: 407-416 |
2001 |
5 | EE | Jing-Jia Liou,
Kwang-Ting Cheng,
Sandip Kundu,
Angela Krstic:
Fast Statistical Timing Analysis By Probabilistic Event Propagation.
DAC 2001: 661-666 |
4 | | Angela Krstic,
Jing-Jia Liou,
Yi-Min Jiang,
Kwang-Ting Cheng:
Delay testing considering crosstalk-induced effects.
ITC 2001: 558-567 |
2000 |
3 | EE | Jing-Jia Liou,
Angela Krstic,
Kwang-Ting Cheng,
Deb Aditya Mukherjee,
Sandip Kundu:
Performance sensitivity analysis using statistical method and its applications to delay.
ASP-DAC 2000: 587-592 |
2 | | Jing-Jia Liou,
Angela Krstic,
Yi-Min Jiang,
Kwang-Ting Cheng:
Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects.
ICCAD 2000: 493-496 |
1 | EE | Jing-Jia Liou,
Kwang-Ting Cheng,
Deb Aditya Mukherjee:
Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis.
VTS 2000: 97-104 |