| 2007 |
|---|
| 10 | | Brendan Mullane,
Chen-Huan Chiang,
Michael Higgins,
Ciaran MacNamee,
Tapan J. Chakraborty,
Thomas B. Cook:
FPGA Prototyping of a Scan Based System-On-Chip Design.
ReCoSoC 2007: 121-126 |
| 2004 |
|---|
| 9 | EE | Chen-Huan Chiang,
Paul J. Wheatley,
Kenneth Y. Ho,
Ken L. Cheung:
Testing and Remote Field Update of Distributed Base Stations in a Wireless Network.
ITC 2004: 711-718 |
| 2002 |
|---|
| 8 | EE | Tapan J. Chakraborty,
Chen-Huan Chiang:
A Novel Fault Injection Method for System Verification Based on FPGA Boundary Scan Architectur.
ITC 2002: 923-929 |
| 2000 |
|---|
| 7 | EE | Chen-Huan Chiang,
Sandeep K. Gupta:
BIST TPG for SRAM cluster interconnect testing at board level.
Asian Test Symposium 2000: 58-65 |
| 6 | | Robert W. Barr,
Chen-Huan Chiang,
Edward L. Wallace:
End-to-end testing for boards and systems using boundary scan.
ITC 2000: 585-592 |
| 5 | EE | Chen-Huan Chiang,
Sandeep K. Gupta:
BIST TPG for Combinational Cluster Interconnect Testing at Board Level.
J. Electronic Testing 16(5): 427-442 (2000) |
| 1998 |
|---|
| 4 | EE | Chen-Huan Chiang,
Sandeep K. Gupta:
BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level.
Asian Test Symposium 1998: 244-252 |
| 1997 |
|---|
| 3 | EE | Chen-Huan Chiang,
Sandeep K. Gupta:
BIST TPG for faults in system backplanes.
ICCAD 1997: 406-413 |
| 2 | EE | Chen-Huan Chiang,
Sandeep K. Gupta:
BIST TPGs for Faults in Board Level Interconnect via Boundary Scan.
VTS 1997: 376-383 |
| 1994 |
|---|
| 1 | EE | Chen-Huan Chiang,
Sandeep K. Gupta:
Random pattern testable logic synthesis.
ICCAD 1994: 125-128 |
