Sandeep Kumar Goel

2009
20	EE	Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty: Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling. IEEE Trans. Computers 58(3): 409-423 (2009)
2007
19	EE	Sandeep Kumar Goel, Erik Jan Marinissen: On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips CoRR abs/0710.4687: (2007)
2006
18	EE	Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke: Fault detection and diagnosis with parity trees for space compaction of test responses. DAC 2006: 1095-1098
17	EE	Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty: Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. DATE 2006: 285-290
16	EE	Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez: Testing and Diagnosis of Power Switches in SOCs. European Test Symposium 2006: 145-150
2005
15	EE	Sandeep Kumar Goel, Erik Jan Marinissen: On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. DATE 2005: 44-49
2004
14	EE	Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel: Automatic generation of breakpoint hardware for silicon debug. DAC 2004: 514-517
13	EE	Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk: Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip. DATE 2004: 108-113
12	EE	Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty: IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. ITC 2004: 1203-1212
2003
11	EE	Sandeep Kumar Goel, Erik Jan Marinissen: Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. DATE 2003: 10738-10741
10	EE	Sandeep Kumar Goel, Erik Jan Marinissen: SOC test architecture design for efficient utilization of test bandwidth. ACM Trans. Design Autom. Electr. Syst. 8(4): 399-429 (2003)
9	EE	Sandeep Kumar Goel, Bart Vermeulen: Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. J. Electronic Testing 19(4): 407-416 (2003)
8	EE	Sandeep Kumar Goel, Erik Jan Marinissen: A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips. J. Electronic Testing 19(4): 425-435 (2003)
2002
7	EE	Sandeep Kumar Goel, Bart Vermeulen: Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. ITC 2002: 1103-1110
6	EE	Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty: Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. ITC 2002: 1159-1168
5	EE	Sandeep Kumar Goel, Erik Jan Marinissen: Effective and Efficient Test Architecture Design for SOCs. ITC 2002: 529-538
4	EE	Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel: Core-Based Scan Architecture for Silicon Debug. ITC 2002: 638-647
3	EE	Sandeep Kumar Goel, Erik Jan Marinissen: Cluster-Based Test Architecture Design for System-on-Chip. VTS 2002: 259-264
2	EE	Bart Vermeulen, Sandeep Kumar Goel: Design for Debug: Catching Design Errors in Digital Chips. IEEE Design & Test of Computers 19(3): 37-45 (2002)
2000
1		Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel: Wrapper design for embedded core test. ITC 2000: 911-920

Coauthor Index

1	Krishnendu Chakrabarty	[6] [12] [17] [20]
2	Kuoshu Chiu	[13]
3	Andreas Glowatz	[18]
4	José Pineda de Gyvez	[16]
5	Friedrich Hapke	[18]
6	Vikram Iyengar	[6]
7	Maurice Lousberg	[1]
8	Erik Jan Marinissen	[1] [3] [5] [6] [8] [10] [11] [12] [13] [15] [17] [19] [20]
9	Maurice Meijer	[16]
10	Toan Nguyen	[13]
11	Steven Oostdijk	[13]
12	Jürgen Schlöffel	[18]
13	Anuja Sehgal	[12] [17] [20]
14	Mohammad Zalfany Urfianto	[14]
15	Bart Vermeulen	[2] [4] [7] [9] [14]
16	Harald P. E. Vranken	[18]
17	Tom Waayers	[4]
18	Yervant Zorian	[1]

Colors in the list of coauthors