| 2008 |
|---|
| 8 | EE | Sankar Gurumurthy,
Ramtilak Vemu,
Jacob A. Abraham,
Suriyaprakash Natarajan:
On efficient generation of instruction sequences to test for delay defects in a processor.
ACM Great Lakes Symposium on VLSI 2008: 279-284 |
| 2006 |
|---|
| 7 | EE | Hangkyu Lee,
Suriyaprakash Natarajan,
Srinivas Patil,
Irith Pomeranz:
Selecting High-Quality Delay Tests for Manufacturing Test and Debug.
DFT 2006: 59-70 |
| 6 | EE | Suriyaprakash Natarajan,
Srinivas Patil,
Sreejit Chakravarty:
Path Delay Fault Simulation on Large Industrial Designs.
VTS 2006: 16-23 |
| 2005 |
|---|
| 5 | EE | Manan Syal,
Michael S. Hsiao,
Suriyaprakash Natarajan,
Sreejit Chakravarty:
Untestable Multi-Cycle Path Delay Faults in Industrial Designs.
Asian Test Symposium 2005: 194-201 |
| 2002 |
|---|
| 4 | EE | Shahin Nazarian,
Hang Huang,
Suriyaprakash Natarajan,
Sandeep K. Gupta,
Melvin A. Breuer:
XIDEN: Crosstalk Target Identification Framework.
ITC 2002: 365-374 |
| 2001 |
|---|
| 3 | | Suriyaprakash Natarajan,
Sandeep K. Gupta,
Melvin A. Breuer:
Switch-level delay test of domino logic circuits.
ITC 2001: 367-376 |
| 1999 |
|---|
| 2 | | Suriyaprakash Natarajan,
Sandeep K. Gupta,
Melvin A. Breuer:
Switch-level delay test.
ITC 1999: 171-180 |
| 1998 |
|---|
| 1 | EE | Suriyaprakash Natarajan,
Melvin A. Breuer,
Sandeep K. Gupta:
Process Variations and their Impact on Circuit Operation.
DFT 1998: 73- |
