2008 |
15 | EE | Hiroshi Takahashi,
Yoshinobu Higami,
Shuhei Kadoyama,
Yuzo Takamatsu,
Koji Yamazaki,
Takashi Aikyo,
Yasuo Sato:
Post-BIST Fault Diagnosis for Multiple Faults.
IEICE Transactions 91-D(3): 771-775 (2008) |
2006 |
14 | EE | Masayasu Fukunaga,
Seiji Kajihara,
Xiaoqing Wen,
Toshiyuki Maeda,
Shuji Hamada,
Yasuo Sato:
A dynamic test compaction procedure for high-quality path delay testing.
ASP-DAC 2006: 348-353 |
13 | EE | Hiroshi Takahashi,
Shuhei Kadoyama,
Yoshinobu Higami,
Yuzo Takamatsu,
Koji Yamazaki,
Takashi Aikyo,
Yasuo Sato:
Effective Post-BIST Fault Diagnosis for Multiple Faults.
DFT 2006: 401-109 |
12 | EE | Yasuo Sato,
Shuji Hamada,
Toshiyuki Maeda,
Atsuo Takatori,
Seiji Kajihara:
A Statistical Quality Model for Delay Testing.
IEICE Transactions 89-C(3): 349-355 (2006) |
2005 |
11 | EE | Yasuo Sato,
Shuji Hamada,
Toshiyuki Maeda,
Atsuo Takatori,
Seiji Kajihara:
Evaluation of the statistical delay quality model.
ASP-DAC 2005: 305-310 |
10 | EE | Seiji Kajihara,
Masayasu Fukunaga,
Xiaoqing Wen,
Toshiyuki Maeda,
Shuji Hamada,
Yasuo Sato:
Path delay test compaction with process variation tolerance.
DAC 2005: 845-850 |
2002 |
9 | EE | Kazumi Hatayama,
Michinobu Nakao,
Yasuo Sato:
At-Speed Built-in Test for Logic Circuits with Multiple Clocks.
Asian Test Symposium 2002: 292-297 |
8 | EE | Kazumi Hatayama,
Michinobu Nakao,
Yoshikazu Kiyoshige,
Koichiro Natsume,
Yasuo Sato,
Takaharu Nagumo:
Application of High-Quality Built-In Test to Industrial Designs.
ITC 2002: 1003-1012 |
7 | EE | Yasuo Sato,
Iwao Yamazaki,
Hiroki Yamanaka,
Toshio Ikeda,
Masahiro Takakura:
A Persistent Diagnostic Technique for Unstable Defects.
ITC 2002: 242-249 |
2001 |
6 | EE | Iwao Yamazaki,
Hiroki Yamanaka,
Toshio Ikeda,
Masahiro Takakura,
Yasuo Sato:
An Approach to Improve the Resolution of Defect-Based Diagnosis.
Asian Test Symposium 2001: 123- |
5 | EE | Michinobu Nakao,
Yoshikazu Kiyoshige,
Kazumi Hatayama,
Yasuo Sato,
Takaharu Nagumo:
Test Generation for Multiple-Threshold Gate-Delay Fault Model.
Asian Test Symposium 2001: 244- |
4 | EE | Yasuo Sato,
M. Sato,
K. Tsutsumida,
Toyohito Ikeya,
M. Kawashima:
A Practical Logic BIST for ASIC Designs.
Asian Test Symposium 2001: 457 |
3 | | Yasuo Sato,
Msaki Kohno,
Toshio Ikeda,
Iwao Yamazaki,
Masato Hamamoto:
An evaluation of defect-oriented test: WELL-controlled low voltage test.
ITC 2001: 1059-1067 |
2000 |
2 | | Yasuo Sato,
Toyohito Ikeya,
Machinobu Nakao,
Takaharu Nagumo:
A BIST approach for very deep sub-micron (VDSM) defects.
ITC 2000: 283-291 |
1991 |
1 | EE | Yasushi Ogawa,
Tsutomu Itoh,
Yoshio Miki,
Tatsuki Ishii,
Yasuo Sato,
Reiji Toyoshima:
Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design.
DAC 1991: 253-258 |