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Yasuo Sato

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2008
15EEHiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato: Post-BIST Fault Diagnosis for Multiple Faults. IEICE Transactions 91-D(3): 771-775 (2008)
2006
14EEMasayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato: A dynamic test compaction procedure for high-quality path delay testing. ASP-DAC 2006: 348-353
13EEHiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato: Effective Post-BIST Fault Diagnosis for Multiple Faults. DFT 2006: 401-109
12EEYasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara: A Statistical Quality Model for Delay Testing. IEICE Transactions 89-C(3): 349-355 (2006)
2005
11EEYasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara: Evaluation of the statistical delay quality model. ASP-DAC 2005: 305-310
10EESeiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato: Path delay test compaction with process variation tolerance. DAC 2005: 845-850
2002
9EEKazumi Hatayama, Michinobu Nakao, Yasuo Sato: At-Speed Built-in Test for Logic Circuits with Multiple Clocks. Asian Test Symposium 2002: 292-297
8EEKazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo: Application of High-Quality Built-In Test to Industrial Designs. ITC 2002: 1003-1012
7EEYasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura: A Persistent Diagnostic Technique for Unstable Defects. ITC 2002: 242-249
2001
6EEIwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Yasuo Sato: An Approach to Improve the Resolution of Defect-Based Diagnosis. Asian Test Symposium 2001: 123-
5EEMichinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo: Test Generation for Multiple-Threshold Gate-Delay Fault Model. Asian Test Symposium 2001: 244-
4EEYasuo Sato, M. Sato, K. Tsutsumida, Toyohito Ikeya, M. Kawashima: A Practical Logic BIST for ASIC Designs. Asian Test Symposium 2001: 457
3 Yasuo Sato, Msaki Kohno, Toshio Ikeda, Iwao Yamazaki, Masato Hamamoto: An evaluation of defect-oriented test: WELL-controlled low voltage test. ITC 2001: 1059-1067
2000
2 Yasuo Sato, Toyohito Ikeya, Machinobu Nakao, Takaharu Nagumo: A BIST approach for very deep sub-micron (VDSM) defects. ITC 2000: 283-291
1991
1EEYasushi Ogawa, Tsutomu Itoh, Yoshio Miki, Tatsuki Ishii, Yasuo Sato, Reiji Toyoshima: Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design. DAC 1991: 253-258

Coauthor Index

1Takashi Aikyo [13] [15]
2Masayasu Fukunaga [10] [14]
3Shuji Hamada [10] [11] [12] [14]
4Masato Hamamoto [3]
5Kazumi Hatayama [5] [8] [9]
6Yoshinobu Higami [13] [15]
7Toshio Ikeda [3] [6] [7]
8Toyohito Ikeya [2] [4]
9Tatsuki Ishii [1]
10Tsutomu Itoh [1]
11Shuhei Kadoyama [13] [15]
12Seiji Kajihara [10] [11] [12] [14]
13M. Kawashima [4]
14Yoshikazu Kiyoshige [5] [8]
15Msaki Kohno [3]
16Toshiyuki Maeda [10] [11] [12] [14]
17Yoshio Miki [1]
18Takaharu Nagumo [2] [5] [8]
19Machinobu Nakao [2]
20Michinobu Nakao [5] [8] [9]
21Koichiro Natsume [8]
22Yasushi Ogawa [1]
23M. Sato [4]
24Hiroshi Takahashi [13] [15]
25Masahiro Takakura [6] [7]
26Yuzo Takamatsu [13] [15]
27Atsuo Takatori [11] [12]
28Reiji Toyoshima [1]
29K. Tsutsumida [4]
30Xiaoqing Wen [10] [14]
31Hiroki Yamanaka [6] [7]
32Iwao Yamazaki [3] [6] [7]
33Koji Yamazaki [13] [15]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)