Kazumi Hatayama

2008
14	EE	Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara: Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. ICCAD 2008: 52-58
2007
13	EE	Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo: Estimation of delay test quality and its application to test generation. ICCAD 2007: 413-417
2006
12	EE	Kazumi Hatayama: Session Abstract. VTS 2006: 200-201
2004
11	EE	Kazumi Hatayama, Rochit Rajsuman: Opportunities with the open architecture test system. ASP-DAC 2004: 334
2002
10	EE	Kazumi Hatayama, Michinobu Nakao, Yasuo Sato: At-Speed Built-in Test for Logic Circuits with Multiple Clocks. Asian Test Symposium 2002: 292-297
9	EE	Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo: Application of High-Quality Built-In Test to Industrial Designs. ITC 2002: 1003-1012
2001
8	EE	Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo: Test Generation for Multiple-Threshold Gate-Delay Fault Model. Asian Test Symposium 2001: 244-
1999
7		Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada: Low overhead test point insertion for scan-based BIST. ITC 1999: 348-357
1997
6	EE	Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto: Application of a Design for Delay Testability Approach to High Speed Logic LSIs. Asian Test Symposium 1997: 112-115
5	EE	Michinobu Nakao, Kazumi Hatayama, Isao Higashi: Accelerated Test Points Selection Method for Scan-Based BIST. Asian Test Symposium 1997: 359-
4	EE	Kazumi Hatayama, Kazunori Hikone, T. Miyazaki, H. Yamada: A practical approach to instruction-based test generation for functional modules of VLSI processors. VTS 1997: 17-23
1995
3	EE	Hiroshi Date, Michinobu Nakao, Kazumi Hatayama: A parallel sequential test generation system DESCARTES based on real-valued logic simulation. Asian Test Symposium 1995: 252-258
1992
2		Kazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi: Sequential Test Generation Based on Real-Value Logic. ITC 1992: 41-48
1989
1		Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama: Enhanced Delay Test Generator for High-Speed Logic LSIs. ITC 1989: 161-165

Coauthor Index

1	Takashi Aikyo	[13] [14]
2	Hiroshi Date	[3]
3	Masayasu Fukunaga	[13]
4	Hiroshi Furukawa	[14]
5	Terumine Hayashi	[1] [2]
6	Isao Higashi	[5]
7	Kazunori Hikone	[2] [4]
8	Kazuhiko Iijima	[7]
9	Mitsuji Ikeda	[1] [2] [6]
10	Shun Ishiyama	[1]
11	Hideaki Ito	[14]
12	Seiji Kajihara	[13] [14]
13	Kuniaki Kishida	[1]
14	Yoshikazu Kiyoshige	[8] [9]
15	Seiji Kobayashi	[7]
16	Kohei Miyase	[14]
17	T. Miyazaki	[4]
18	Shohei Morishima	[13]
19	Takaharu Nagumo	[8] [9]
20	Michinobu Nakao	[3] [5] [7] [8] [9] [10]
21	Koichiro Natsume	[9]
22	Kenji Noda	[14]
23	Rochit Rajsuman	[11]
24	Yoriyuki Sakamoto	[6]
25	Yasuo Sato	[8] [9] [10]
26	Masahiro Takakura	[1] [6]
27	Seiji Terada	[7]
28	Satoshi Uchiyama	[6]
29	Xiaoqing Wen	[13] [14]
30	H. Yamada	[4]
31	Masahiro Yamamoto	[13]
32	Yuta Yamato	[14]

Colors in the list of coauthors