Jayanta Bhadra

2009
25	EE	Di Wang, Vyas Venkataraman, Zhen Wang, Wei Qin, Hangsheng Wang, Mrinal Bose, Jayanta Bhadra: Accelerating multi-party scheduling for transaction-level modeling. ACM Great Lakes Symposium on VLSI 2009: 339-344
24	EE	Mrinal Bose, Prashant Naphade, Jayanta Bhadra, Hillel Miller: An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs. ISQED 2009: 377-381
2008
23	EE	Jayanta Bhadra, Ekaterina Trofimova, Magdy S. Abadir: Validating Power ArchitectureTM Technology-Based MPSoCs Through Executable Specifications. IEEE Trans. VLSI Syst. 16(4): 388-396 (2008)
2007
22		Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra: Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA IEEE Computer Society 2007
21	EE	Sandip Ray, Jayanta Bhadra: A Mechanized Refinement Framework for Analysis of Custom Memories. FMCAD 2007: 239-242
20	EE	Charles H.-P. Wen, Li-C. Wang, Jayanta Bhadra: An incremental learning framework for estimating signal controllability in unit-level verification. ICCAD 2007: 250-257
19	EE	Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang: Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques. IEEE Design & Test of Computers 24(2): 110-111 (2007)
18	EE	Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Sandip Ray: A Survey of Hybrid Techniques for Functional Verification. IEEE Design & Test of Computers 24(2): 112-122 (2007)
2006
17		Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra: Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA IEEE Computer Society 2006
16	EE	Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir: Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. MTV 2006: 33-36
2005
15	EE	Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova: Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. MTV 2005: 111-118
14	EE	Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham: A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor. Formal Methods in System Design 27(1-2): 67-112 (2005)
2004
13	EE	Alper Sen, Vijay K. Garg, Jacob A. Abraham, Jayanta Bhadra: Formal Verification of a System-on-Chip Using Computation Slicing. ITC 2004: 810-819
12	EE	Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham: Towards The Complete Elimination of Gate/Switch Level Simulations. VLSI Design 2004: 115-
11	EE	Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir: Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation. IEEE Design & Test of Computers 21(6): 494-502 (2004)
2003
10	EE	Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir: A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits. MTV 2003: 32-37
9	EE	Kyoil Kim, Jacob A. Abraham, Jayanta Bhadra: Model Checking of Security Protocols with Pre-configuration. WISA 2003: 1-15
8	EE	Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra, Raghuram S. Tupuri: A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages. J. Electronic Testing 19(2): 149-160 (2003)
2002
7	EE	Jayanta Bhadra, Narayanan Krishnamurthy: Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits. ITC 2002: 213-222
6	EE	Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra: Program Slicing for Hierarchical Test Generation. VTS 2002: 237-246
5	EE	Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham: Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? VTS 2002: 275-280
2001
4	EE	Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir: Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation. CHARME 2001: 386-402
3	EE	Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham: Full chip false timing path identification: applications to the PowerPCTM microprocessors. DATE 2001: 514-519
2000
2	EE	Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham: Automatic Validation Test Generation Using Extracted Control Models. VLSI Design 2000: 312-
1999
1	EE	Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham: Improving Witness Search Using Orders on States. ICCD 1999: 452-457

Coauthor Index

1	Magdy S. Abadir	[3] [4] [5] [10] [11] [12] [15] [16] [17] [18] [19] [22] [23]
2	Jacob A. Abraham	[1] [2] [3] [4] [5] [6] [8] [9] [12] [13] [14]
3	Mrinal Bose	[24] [25]
4	David Burgess	[15]
5	Vijay K. Garg	[13]
6	Kyoil Kim	[9]
7	Heon-Mo Koo	[16]
8	Narayanan Krishnamurthy	[5] [7] [10] [11] [12]
9	Andrew K. Martin	[4] [14]
10	Hillel Miller	[24]
11	Prabhat Mishra	[16]
12	Prashant Naphade	[24]
13	Wei Qin	[25]
14	Sandip Ray	[18] [21]
15	Alper Sen	[13]
16	Robert W. Sumners	[1] [2]
17	Ekaterina Trofimova	[15] [23]
18	Raghuram S. Tupuri	[8]
19	Vivekananda M. Vedula	[6] [8]
20	Vyas Venkataraman	[25]
21	Di Wang	[25]
22	Hangsheng Wang	[25]
23	Li-C. Wang	[17] [18] [19] [20] [22]
24	Zhen Wang	[25]
25	Charles H.-P. Wen	[20]
26	Jing Zeng	[3]