| 2004 |
|---|
| 11 | EE | Saman Adham,
Benoit Nadeau-Dostie:
A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs.
MTDT 2004: 98-101 |
| 2002 |
|---|
| 10 | EE | Stephen K. Sunter,
Benoit Nadeau-Dostie:
Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost.
ITC 2002: 446-455 |
| 1999 |
|---|
| 9 | | Benoit Nadeau-Dostie,
Jean-Francois Cote,
Harry Hulvershorn,
Stephen Pateras:
An embedded technique for at-speed interconnect testing.
ITC 1999: 431-438 |
| 8 | EE | Samir Boubezari,
Eduard Cerny,
Bozena Kaminska,
Benoit Nadeau-Dostie:
Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1327-1340 (1999) |
| 1996 |
|---|
| 7 | | Bernd Könemann,
Ben Bennetts,
Najmi T. Jarwala,
Benoit Nadeau-Dostie:
Built-In Self-Test: Assuring System Integrity.
IEEE Computer 29(11): 39-45 (1996) |
| 1995 |
|---|
| 6 | | Benoit Nadeau-Dostie,
Harry Hulvershorn,
Saman Adham:
A New Hardware Fault Insertion Scheme for System Diagnostics Verification.
ITC 1995: 994-1002 |
| 1994 |
|---|
| 5 | EE | Benoit Nadeau-Dostie,
Dwayne Burek,
Abu S. M. Hassan:
ScanBist: A Multifrequency Scan-Based BIST Method.
IEEE Design & Test of Computers 11(1): 7-17 (1994) |
| 1992 |
|---|
| 4 | | Benoit Nadeau-Dostie,
Dwayne Burek,
Abu S. M. Hassan:
ScanBIST: A Multi-frequency Scan-based BIST Method.
ITC 1992: 506-513 |
| 3 | EE | Abu S. M. Hassan,
Vinod K. Agarwal,
Benoit Nadeau-Dostie,
Janusz Rajski:
BIST of PCB interconnects using boundary-scan architecture.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(10): 1278-1288 (1992) |
| 1990 |
|---|
| 2 | EE | Benoit Nadeau-Dostie,
Allan Silburt,
Vinod K. Agarwal:
Serial Interfacing for Embedded-Memory Testing.
IEEE Design & Test of Computers 7(2): 52-63 (1990) |
| 1989 |
|---|
| 1 | | Abu S. M. Hassan,
Vinod K. Agarwal,
Janusz Rajski,
Benoit Nadeau-Dostie:
Testing of Glue Logic Interconnects Using Boundary Scan Architecture.
ITC 1989: 700-711 |
