| 2004 |
| 18 | EE | Takahiro J. Yamaguchi,
Mani Soma,
Jim Nissen,
David Halter,
Rajesh Raina,
Masahiro Ishida:
Skew measurements in clock distribution circuits using an analytic signal method.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 997-1009 (2004) |
| 2002 |
| 17 | EE | John Gatej,
Lee Song,
Carol Pyron,
Rajesh Raina,
Tom Munns:
valuating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits.
ITC 2002: 1040-1049 |
| 16 | EE | Dawit Belete,
Ashutosh Razdan,
William Schwarz,
Rajesh Raina,
Christopher Hawkins,
Jeff Morehead:
Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor .
ITC 2002: 1111-1119 |
| 15 | EE | Mani Soma,
Welela Haileselassie,
Jessica Yan,
Rajesh Raina:
A Wavelet-Based Timing Parameter Extraction Method.
ITC 2002: 120-128 |
| 14 | EE | B. Bailey,
A. Metayer,
B. Svrcek,
Nandu Tendolkar,
E. Wolf,
Eric Fiene,
Mike Alexander,
Rick Woltenberg,
Rajesh Raina:
Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture.
ITC 2002: 574-583 |
| 13 | EE | Nandu Tendolkar,
Rajesh Raina,
Rick Woltenberg,
Xijiang Lin,
Bruce Swanson,
Greg Aldrich:
Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture.
VTS 2002: 3-8 |
| 2001 |
| 12 | EE | Takahiro J. Yamaguchi,
Mani Soma,
Jim Nissen,
David Halter,
Rajesh Raina,
Masahiro Ishida:
Testing clock distribution circuits using an analytic signal method.
ITC 2001: 323-331 |
| 11 | EE | Takahiro J. Yamaguchi,
Masahiro Ishida,
Mani Soma,
David Halter,
Rajesh Raina,
Jim Nissen:
A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals.
VTS 2001: 102-110 |
| 10 | EE | Jay Bedsole,
Rajesh Raina,
Al Crouch,
Magdy S. Abadir:
Very Low Cost Testers: Opportunities and Challenges.
IEEE Design & Test of Computers 18(5): 60-69 (2001) |
| 2000 |
| 9 | | Rajesh Raina,
Robert Bailey,
Dawit Belete,
Vikram Khosa,
Robert F. Molyneaux,
Javier Prado,
Ashutosh Razdan:
DFT advances in Motorola's Next-Generation 74xx PowerPCTM microprocessor.
ITC 2000: 131-140 |
| 8 | | Takahiro J. Yamaguchi,
Mani Soma,
David Halter,
Jim Nissen,
Rajesh Raina,
Masahiro Ishida,
Toshifumi Watanabe:
Jitter measurements of a PowerPCTM microprocessor using an analytic signal method.
ITC 2000: 955-964 |
| 7 | EE | Nandu Tendolkar,
Robert F. Molyneaux,
Carol Pyron,
Rajesh Raina:
At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor.
VTS 2000: 3-8 |
| 1999 |
| 6 | | Carol Pyron,
Mike Alexander,
James Golab,
George Joos,
Bruce Long,
Robert F. Molyneaux,
Rajesh Raina,
Nandu Tendolkar:
DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor.
ITC 1999: 137-146 |
| 5 | | Magdy S. Abadir,
Rajesh Raina:
Design-for-test methodology for Motorola PowerPC microprocessors.
ITC 1999: 810-819 |
| 1998 |
| 4 | EE | Rajesh Raina,
Robert F. Molyneaux:
Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches.
Great Lakes Symposium on VLSI 1998: 222-229 |
| 1997 |
| 3 | EE | Rajesh Raina,
Robert Bailey,
Charles Njinda,
Robert F. Molyneaux,
Charlie Beh:
Efficient Testing of Clock Regenerator Circuits in Scan Designs.
DAC 1997: 95-100 |
| 2 | | Rajesh Raina,
Charles Njinda,
Robert F. Molyneaux:
How Seriously Do You Take Your Possible-Detect Faults?
ITC 1997: 819-828 |
| 1996 |
| 1 | EE | James Monaco,
David Holloway,
Rajesh Raina:
Functional Verification Methodology for the PowerPC 604 Microprocessor.
DAC 1996: 319-324 |