IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 16

Volume 16, Number 1, January 2008

• Toomas P. Plaks:
  Guest Editorial Special Section on Configurable Computing Design- I: High-Level Reconfiguration. 1-2
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• Gerard K. Rauwerda, Paul M. Heysters, Gerard J. M. Smit:
  Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware. 3-13
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• Mitchell J. Myjak, José G. Delgado-Frias:
  A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance. 14-23
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• Vincent Nollet, Prabhat Avasare, Hendrik Eeckhaut, Diederik Verkest, Henk Corporaal:
  Run-Time Management of a MPSoC Containing FPGA Fabric Tiles. 24-33
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• David L. Andrews, Ron Sass, Erik Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp:
  Achieving Programming Model Abstractions for Reconfigurable Computing. 34-44
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• Jingzhao Ou, Viktor K. Prasanna:
  A Cooperative Management Scheme for Power Efficient Implementations of Real-Time Operating Systems on Soft Processors. 45-56
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• Sherif Yusuf, Wayne Luk, Morris Sloman, Naranker Dulay, Emil C. Lupu, Geoffrey Brown:
  Reconfigurable Architecture for Network Flow Analysis. 57-65
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• Justin L. Tripp, Maya Gokhale, Anders A. Hansson:
  A Case Study of Hardware/Software Partitioning of Traffic Simulation on the Cray XD1. 66-74
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• Sami Khawam, Ioannis Nousias, Mark Milward, Ying Yi, Mark Muir, Tughrul Arslan:
  The Reconfigurable Instruction Cell Array. 75-85
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• Kanak Agarwal, Sani R. Nassif:
  The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies. 86-97
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• Irith Pomeranz, Sudhakar M. Reddy:
  Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects. 98-107
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• C.-Y. Chang, H.-M. Chen:
  Design Migration From Peripheral ASIC Design to Area-I/O Flip-Chip Design by Chip I/O Planning and Legalization. 108-112
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Volume 16, Number 2, February 2008

• Toomas P. Plaks:
  Guest Editorial Special Section on Configurable Computing Design-II: Hardware Level Reconfiguration. 113-114
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• Paul Beckett:
  A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors. 115-123
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• Yan Lin, Lei He, Mike Hutton:
  Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs. 124-133
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• Peter Zipf:
  Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays. 134-143
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• Guy Gogniat, Tilman Wolf, Wayne P. Burleson, Jean-Philippe Diguet, Lilian Bossuet, Romain Vaslin:
  Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective. 144-155
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• Ioannis Sourdis, Dionisios N. Pnevmatikatos, Stamatis Vassiliadis:
  Scalable Multigigabit Pattern Matching for Packet Inspection. 156-166
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• Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna:
  Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores. 167-176
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• Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert:
  Architectural Modifications to Enhance the Floating-Point Performance of FPGAs. 177-187
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• Xinming Huang, Cao Liang, Jing Ma:
  System Architecture and Implementation of MIMO Sphere Decoders on FPGA. 188-197
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• W. N. Chelton, Mohammed Benaissa:
  Fast Elliptic Curve Cryptography on FPGA. 198-205
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• Jie Gu, John Keane, Sachin S. Sapatnekar, Chris H. Kim:
  Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property. 206-209
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• Saralees Nadarajah, Samuel Kotz:
  Exact Distribution of the Max/Min of Two Gaussian Random Variables. 210-212
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Volume 16, Number 3, March 2008

• Xiaofeng Wu, Vassilios A. Chouliaras, José L. Núñez-Yáñez, R. M. Goodall:
  A Novel Delta Sigma Control System Processor and Its VLSI Implementation. 217-228
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• Eriko Nurvitadhi, Jumnit Hong, Shih-Lien Lu:
  Active Cache Emulator. 229-240
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• Ruiming Chen, Hai Zhou:
  Fast Estimation of Timing Yield Bounds for Process Variations. 241-248
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• Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
  Body Bias Voltage Computations for Process and Temperature Compensation. 249-262
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• Achintya Halder, Soumendu Bhattacharya, Abhijit Chatterjee:
  System-Level Specification Testing Of Wireless Transceivers. 263-276
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• Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ding-Yeong Wang, Yuan-Jen Lee, Ming-Jer Kao:
  Write Disturbance Modeling and Testing for MRAM. 277-288
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• Hyuk-Jun Lee, Eui-Young Chung:
  Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory. 289-301
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• Ke Xu, Chiu-Sing Choy:
  A Power-Efficient and Self-Adaptive Prediction Engine for H.264/AVC Decoding. 302-313
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• Srinivasa R. Sridhara, Ganesh Balamurugan, Naresh R. Shanbhag:
  Joint Equalization and Coding for On-Chip Bus Communication. 314-318
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• C. Popa:
  Improved Accuracy Pseudo-Exponential Function Generator With Applications in Analog Signal Processing. 318-321
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• Youngmoon Choi, Earl E. Swartzlander Jr.:
  Speculative Carry Generation With Prefix Adder. 321-326
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• Sabyasachi Das, Sunil P. Khatri:
  A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic. 326-331
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• Shanq-Jang Ruan, Chi-Yu Wu, Jui-Yuan Hsieh:
  Low Power Design of Precomputation-Based Content-Addressable Memory. 331-335
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Volume 16, Number 4, April 2008

• I. Harris, D. Pradhan:
  Guest Editorial Special Section on Design Verification and Validation. 337-338
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• Deepak Mathaikutty, Sreekumar V. Kodakara, Ajit Dingankar, Sandeep K. Shukla, David J. Lilja:
  MMV: A Metamodeling Based Microprocessor Validation Environment. 339-352
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• Panagiotis Manolios, Sudarshan K. Srinivasan:
  A Refinement-Based Compositional Reasoning Framework for Pipelined Machine Verification. 353-364
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• Shih-Chieh Wu, Chun-Yao Wang, Yung-Chih Chen:
  Novel Probabilistic Combinational Equivalence Checking. 365-375
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• Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu:
  Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra. 376-387
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• Jayanta Bhadra, Ekaterina Trofimova, Magdy S. Abadir:
  Validating Power Architecture^TM Technology-Based MPSoCs Through Executable Specifications. 388-396
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• Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian:
  IEEE Standard 1500 Compliance Verification for Embedded Cores. 397-407
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• Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti, Vivekananda M. Vedula, K. S. Maneperambil:
  Automatic Constraint Based Test Generation for Behavioral HDL Models. 408-421
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• David de Andrés, Juan Carlos Ruiz, Daniel Gil, Pedro Gil:
  Fault Emulation for Dependability Evaluation of VLSI Systems. 422-431
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• P. Y. Paik, Vamsee K. Pamula, Krishnendu Chakrabarty:
  Adaptive Cooling of Integrated Circuits Using Digital Microfluidics. 432-443
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• Yuh-Fang Tsai, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin:
  Design Space Exploration for 3-D Cache. 444-455
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• Jonggab Kil, Jie Gu, Chris H. Kim:
  A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting. 456-465
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• Dongwan Shin, Andreas Gerstlauer, Rainer Dömer, Daniel Gajski:
  An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors. 466-475
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• Eric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge:
  Multi-Mechanism Reliability Modeling and Management in Dynamic Systems. 476-487
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• Zhiyu Liu, Volkan Kursun:
  Characterization of a Novel Nine-Transistor SRAM Cell. 488-492
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Volume 16, Number 5, May 2008

• Katherine Compton, Scott Hauck:
  Automatic Design of Reconfigurable Domain-Specific Flexible Cores. 493-503
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• Heng Tan, Ronald F. DeMara:
  A Multilayer Framework Supporting Autonomous Run-Time Partial Reconfiguration. 504-516
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• Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel:
  A Compact and Accurate Gaussian Variate Generator. 517-527
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• Sanjukta Bhanja, Sudeep Sarkar:
  Thermal Switching Error Versus Delay Tradeoffs in Clocked QCA Circuits. 528-541
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• Daniele Rossi, André K. Nieuwland, Steven V. E. S. van Dijk, Richard P. Kleihorst, Cecilia Metra:
  Power Consumption of Fault Tolerant Busses. 542-553
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• Banit Agrawal, Timothy Sherwood:
  Ternary CAM Power and Delay Model: Extensions and Uses. 554-564
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• Yongmei Dai, Zhiyuan Yan, Ning Chen:
  Optimal Overlapped Message Passing Decoding of Quasi-Cyclic LDPC Codes. 565-578
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• Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton:
  Practical Asynchronous Interconnect Network Design. 579-588
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• Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen:
  Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime. 589-593
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• Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng:
  A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic. 594-598
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• John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim:
  Stack Sizing for Optimal Current Drivability in Subthreshold Circuits. 598-602
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• Zhenyu Gu, Changyun Zhu, Li Shang, Robert P. Dick:
  Application-Specific MPSoC Reliability Optimization. 603-608
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Volume 16, Number 6, June 2008

• Diana Marculescu, Jörg Henkel:
  Guest Editorial Special Section on Low-Power Electronics and Design. 609-610
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• Dongsheng Ma, Feng Luo:
  Robust Multiple-Phase Switched-Capacitor DC-DC Power Converter With Digital Interleaving Regulation Scheme. 611-619
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• Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto:
  Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. 620-627
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• Elham Safi, Andreas Moshovos, Andreas G. Veneris:
  L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture. 628-638
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• Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
  Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers. 639-649
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• Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose:
  Selective Writeback: Reducing Register File Pressure and Energy Consumption. 650-661
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• Wonbok Lee, Kimish Patel, Massoud Pedram:
  GOP-Level Dynamic Thermal Management in MPEG-2 Decoding. 662-672
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• Prashant Singh, Jae-sun Seo, David Blaauw, Dennis Sylvester:
  Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect. 673-677
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• Jianwei Zhang, Yizheng Ye, Bin-Da Liu:
  A Current-Recycling Technique for Shadow-Match-Line Sensing in Content-Addressable Memories. 677-682
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• Azadeh Davoodi, Ankur Srivastava:
  Variability Driven Gate Sizing for Binning Yield Optimization. 683-692
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• Juan Carlos Baraza, Joaquin Gracia, Sara Blanc, Daniel Gil, Pedro J. Gil:
  Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code. 693-706
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• Rohit Singhal, Gwan Choi, Rabi N. Mahapatra:
  Data Handling Limits of On-Chip Interconnects. 707-713
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• Chong Zhao, Yi Zhao, Sujit Dey:
  Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits. 714-724
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• Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Stamatis Vassiliadis:
  Test Set Development for Cache Memory in Modern Microprocessors. 725-732
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• Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
  Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices. 733-744
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• Kaveh Shakeri, James D. Meindl:
  Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method. 745-754
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• Ying-Yen Chen, Jing-Jia Liou:
  Diagnosis Framework for Locating Failed Segments of Path Delay Faults. 755-765
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• Sampo Tuuna, Li-Rong Zheng, Jouni Isoaho, Hannu Tenhunen:
  Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid. 766-770
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• Shizhong Mei:
  Timing Jitter and Power Spectral Density of Random Walk Noise in VCO. 770-774
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• Mohamed Anane, Hamid Bessalah, Mohamed Issad, Nadjia Anane, Hassen Salhi:
  Higher Radix and Redundancy Factor for Floating Point SRT Division. 774-779
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Volume 16, Number 7, July 2008

• Kieran McLaughlin, Sakir Sezer, Holger Blume, Xin Yang, Friederich Kupzog, Tobias G. Noll:
  A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling. 781-791
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• Deepak Mathaikutty, Sandeep K. Shukla:
  MCF: A Metamodeling-Based Component Composition Framework - Composing SystemC IPs for Executable System Models. 792-805
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• Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy:
  Profit Aware Circuit Design Under Process Variations Considering Speed Binning. 806-815
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• Brian Swahn, Soha Hassoun:
  Electro-Thermal Analysis of Multi-Fin Devices. 816-829
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• Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner:
  Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers. 830-836
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• Giorgos Dimitrakopoulos, Costas Galanopoulos, Christos Mavrokefalidis, Dimitris Nikolos:
  Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units. 837-850
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• Behnam Amelifard, Farzan Fallah, Massoud Pedram:
  Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology. 851-860
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• Shengqi Yang, Wenping Wang, Tiehan Lv, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie:
  Case Study of Reliability-Aware and Low-Power Design. 861-873
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• David Choi, Kyu Choi, John D. Villasenor:
  New Non-Volatile Memory Structures for FPGA Architectures. 874-881
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• Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arifur Rahman:
  Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues. 882-893
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• Mikhail Popovich, Michael Sotman, Avinoam Kolodny, Eby G. Friedman:
  Effective Radii of On-Chip Decoupling Capacitors. 894-907
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• Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny:
  On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits. 908-921
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• Xiaomeng Shi, Kiat Seng Yeo, Jianguo Ma, Manh Anh Do, Erping Li:
  Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs. 922-926
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• Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
  Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains. 926-931
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• Irith Pomeranz, Sudhakar M. Reddy:
  Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion. 931-936
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• Chua-Chin Wang, Chi-Chun Huang, Jian-Ming Huang, Chih-Yi Chang, Chih-Peng Li:
  ZigBee 868/915-MHz Modulator/Demodulator for Wireless Personal Area Network. 936-939
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Volume 16, Number 8, August 2008

• Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta:
  Satisfiability Models for Maximum Transition Power. 941-951
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• Han-Lin Li, Chia-Lin Yang, Hung-Wei Tseng:
  Energy-Aware Flash Memory Management in Virtual Memory System. 952-964
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• Yen-Jen Chang, Yuan-Hong Liao:
  Hybrid-Type CAM Design for Both Power and Performance Efficiency. 965-974
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• Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow:
  A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing. 975-984
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• Daler N. Rakhmatov:
  Energy Budget Approximations for Battery-Powered Systems With a Fixed Schedule of Active Intervals. 985-998
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• Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis:
  Cost-Efficient SHA Hardware Accelerators. 999-1008
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• Lei Wang, Niral Patel:
  Improving Error Tolerance for Multithreaded Register Files. 1009-1020
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• Zhonghai Lu, Axel Jantsch:
  TDM Virtual-Circuit Configuration for Network-on-Chip. 1021-1034
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• Pallav Gupta, Rui Zhang, Niraj K. Jha:
  Automatic Test Generation for Combinational Threshold Logic Networks. 1035-1045
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• Dan Zhao, Yi Wang:
  MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip. 1046-1057
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• Chin-Teng Lin, Yuan-Chu Yu, Lan-Da Van:
  Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor. 1058-1071
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• Chung-Ming Chen, Chung-Ho Chen:
  Configurable VLSI Architecture for Deblocking Filter in H.264/AVC. 1072-1082
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• Joshua Noseworthy, Miriam Leeser:
  Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA. 1083-1090
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• Miriam J. Akl, Magdy A. Bayoumi:
  Transition Skew Coding for Global On-Chip Interconnect. 1091-1096
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• S. Kwok, E. Y. Lam:
  Effective Uses of FPGAs for Brute-Force Attack on RC4 Ciphers. 1096-1100
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Volume 16, Number 9, September 2008

• Yu Wang, Ku He, Rong Luo, Hui Wang, Huazhong Yang:
  Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits. 1101-1113
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• Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry:
  A Comparative Study Between Static and Dynamic Sleep Signal Generation Techniques for Leakage Tolerant Designs. 1114-1126
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• Ayse Kivilcim Coskun, T. T. Rosing, Keith Whisnant, Kenny C. Gross:
  Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs. 1127-1140
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• Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien:
  Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing. 1141-1150
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• Ming-Der Shieh, Jun-Hong Chen, Hao-Hsuan Wu, Wen-Ching Lin:
  A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem. 1151-1161
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• Kimmo U. Järvinen, Jorma Skyttä:
  On Parallelization of High-Speed Processors for Elliptic Curve Cryptography. 1162-1175
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• Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla:
  A Trace-Based Framework for Verifiable GALS Composition of IPs. 1176-1186
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• Takefumi Yoshikawa, T. Hirata, Tsuyoshi Ebuchi, Toru Iwata, Yukio Arima, Hiroyuki Yamauchi:
  An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics. 1187-1198
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• Praveen Bhojwani, Rabi N. Mahapatra:
  Robust Concurrent Online Testing of Network-on-Chip-Based SoCs. 1199-1209
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• Sándor P. Fekete, Jan van der Veen, Ali Ahmadinia, Diana Göhringer, Mateusz Majer, Jürgen Teich:
  Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device. 1210-1219
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• A. Kapoor, Nikhil Jayakumar, Sunil P. Khatri:
  Dynamically De-Skewable Clock Distribution Methodology. 1220-1229
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• Charbel J. Akl, Magdy A. Bayoumi:
  Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion. 1230-1239
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• Dongsheng Ma, J. Wang, Minkyu Song:
  Adaptive On-Chip Power Supply With Robust One-Cycle Control Technique. 1240-1243
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• A. Elyada, Ran Ginosar, U. Weiser:
  Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors. 1243-1248
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• Ioannis Voyiatzis:
  An Accumulator-Based Compaction Scheme For Online BIST of RAMs. 1248-1251
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• Lin Zhang, A. Carpenter, B. Ciftcioglu, A. Garg, M. Huang, Hui Wu:
  Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors. 1251-1256
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Volume 16, Number 10, October 2008

• Paolo Ienne, P. Petrov:
  Guest Editorial Special Section on Application Specific Processors. 1257-1258
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• Paolo Bonzini, Laura Pozzi:
  Recurrence-Aware Instruction Set Selection for Extensible Embedded Processors. 1259-1267
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• Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung:
  Outer Loop Pipelining for Application Specific Datapaths in FPGAs. 1268-1280
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• Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid:
  A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors. 1281-1294
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• Lars Bauer, Muhammad Shafique, Jörg Henkel:
  Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation. 1295-1308
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• Timo Vogt, Norbert Wehn:
  A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR Environment. 1309-1320
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• P. Dang:
  High Performance Architecture of an Application Specific Processor for the H.264 Deblocking Filter. 1321-1334
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• Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf:
  A Processing Path Dispatcher in Network Processor MPSoCs. 1335-1345
  Electronic Edition (link) BibTeX
• Hong Lu, A. Forin:
  Automatic Processor Customization for Zero-Overhead Online Software Verification. 1346-1357
  Electronic Edition (link) BibTeX
• Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu:
  Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel. 1358-1371
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• Saihua Lin, Huazhong Yang, Rong Luo:
  A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems. 1372-1384
  Electronic Edition (link) BibTeX
• Bing-Fei Wu, Hsin-Yuan Peng, Tung-Lung Yu:
  Efficient Hierarchical Motion Estimation Algorithm and Its VLSI Architecture. 1385-1398
  Electronic Edition (link) BibTeX
• Girish Varatkar, Naresh R. Shanbhag:
  Error-Resilient Motion Estimation Architecture. 1399-1412
  Electronic Edition (link) BibTeX
• Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
  Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication. 1413-1426
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Volume 16, Number 11, November 2008

• Zhanglei Wang, Krishnendu Chakrabarty:
  Test Data Compression Using Selective Encoding of Scan Slices. 1429-1440
  Electronic Edition (link) BibTeX
• Dimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, M. Maniatakos, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi:
  Systematic Software-Based Self-Test for Pipelined Processors. 1441-1453
  Electronic Edition (link) BibTeX
• Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet:
  Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis. 1454-1464
  Electronic Edition (link) BibTeX
• Zexin Pan, B. Earl Wells:
  Hardware Supported Task Scheduling on Dynamically Reconfigurable SoC Architectures. 1465-1474
  Electronic Edition (link) BibTeX
• Benjamin Carrión Schäfer, Taewhan Kim:
  Hotspots Elimination and Temperature Flattening in VLSI Circuits. 1475-1487
  Electronic Edition (link) BibTeX
• Sheng-Chih Lin, Kaustav Banerjee:
  A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies. 1488-1498
  Electronic Edition (link) BibTeX
• Jorge Campos, Hussain Al-Asaad:
  A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions. 1499-1512
  Electronic Edition (link) BibTeX
• Stephan Henzler, Siegmar Koeppe:
  Design and Application of Power Optimized High-Speed CMOS Frequency Dividers. 1513-1520
  Electronic Edition (link) BibTeX
• Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton:
  GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. 1521-1534
  Electronic Edition (link) BibTeX
• Kamran Farzan, David A. Johns:
  A Robust 4-PAM Signaling Scheme for Inter-Chip Links Using Coding in Space. 1535-1544
  Electronic Edition (link) BibTeX
• Manuel G. Gericota, Gustavo R. Alves, Miguel L. Silva, José M. Ferreira:
  Reliability and Availability in Reconfigurable Computing: A Basis for a Common Solution. 1545-1558
  Electronic Edition (link) BibTeX
• K. Takeuchi, A. Yoshikawa, M. Komoda, K. Kotani, H. Matsushita, Y. Katsuki, Y. Yamamoto, T. Sato:
  Clock-Skew Test Module for Exploring Reliable Clock-Distribution Under Process and Global Voltage-Temperature Variations. 1559-1566
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• Jyu-Yuan Lai, Chih-Tsun Huang:
  Elixir: High-Throughput Cost-Effective Dual-Field Processors and the Design Framework for Elliptic Curve Cryptography. 1567-1580
  Electronic Edition (link) BibTeX
• Xiongfei Meng, Resve A. Saleh, Karim Arabi:
  Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS. 1581-1588
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Volume 16, Number 12, December 2008

• Sungjoon Jung, Tag Gon Kim:
  An Operation and Interconnection Sharing Algorithm for Reconfiguration Overhead Reduction Using Static Partial Reconfiguration. 1589-1595
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• Nazish Aslam, Mark Milward, Ahmet T. Erdogan, Tughrul Arslan:
  Code Compression and Decompression for Coarse-Grain Reconfigurable Architectures. 1596-1608
  Electronic Edition (link) BibTeX
• Hao Yu, Yiyu Shi, Lei He, Tanay Karnik:
  Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power. 1609-1619
  Electronic Edition (link) BibTeX
• Tae-Hwan Kim, In-Cheol Park:
  Low-Power and High-Accurate Synchronization for IEEE 802.16d Systems. 1620-1630
  Electronic Edition (link) BibTeX
• M. Bennaser, Yao Guo, Csaba Andras Moritz:
  Data Memory Subsystem Resilient to Process Variations. 1631-1638
  Electronic Edition (link) BibTeX
• D. E. Khalil, Muhammad M. Khellah, Nam-Sung Kim, Yehea I. Ismail, Tanay Karnik, V. K. De:
  Accurate Estimation of SRAM Dynamic Stability. 1639-1647
  Electronic Edition (link) BibTeX
• B. Taskin, Bo Hong:
  Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking. 1648-1656
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• Jente B. Kuang, Keunwoo Kim, Ching-Te Chuang, Hung C. Ngo, F. H. Gebara, Kevin J. Nowka:
  Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies. 1657-1665
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• Jason D. Bakos, Panormitis E. Elenis:
  A Special-Purpose Architecture for Solving the Breakpoint Median Problem. 1666-1676
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• O. Katz, D. A. Ramon, Israel A. Wagner:
  A Robust Random Number Generator Based on a Differential Current-Mode Chaos. 1677-1686
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• Cheng Jia, Linda S. Milor:
  A BIST Circuit for DLL Fault Detection. 1687-1695
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• Talal Bonny, Jörg Henkel:
  Efficient Code Compression for Embedded Processors. 1696-1707
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• I-Chyn Wey, You-Gang Chen, An-Yeu Wu:
  Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits. 1708-1712
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• Minsik Cho, David Z. Pan:
  Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs. 1713-1717
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• Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
  Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs. 1717-1721
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• Ignacio Bravo, Manuel Mazo, José Luis Lázaro, Pedro Jiménez, Alfredo Gardel, Marta Marrón:
  Novel HW Architecture Based on FPGAs Oriented to Solve the Eigen Problem. 1722-1725
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• Eric Quinnell, Earl E. Swartzlander Jr., Carl Lemonds:
  Bridge Floating-Point Fused Multiply-Add Design. 1727-1731
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