| 2009 |
|---|
| 23 | EE | Bin Zhou,
Yizheng Ye,
Zhao-lin Li,
Xin-chun Wu,
Rui Ke:
A new low power test pattern generator using a variable-length ring counter.
ISQED 2009: 248-252 |
| 2008 |
|---|
| 22 | EE | Qingli Zhang,
Jinxiang Wang,
Yizheng Ye:
Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters.
VLSI Design 2008: 377-382 |
| 21 | EE | Jianwei Zhang,
Yizheng Ye,
Bin-Da Liu:
A Current-Recycling Technique for Shadow-Match-Line Sensing in Content-Addressable Memories.
IEEE Trans. VLSI Syst. 16(6): 677-682 (2008) |
| 2007 |
|---|
| 20 | EE | Bin Zhou,
Yizheng Ye,
Yong-sheng Wang:
Simultaneous reduction in test data volume and test time for TRC-reseeding.
ACM Great Lakes Symposium on VLSI 2007: 49-54 |
| 2006 |
|---|
| 19 | EE | Qingli Zhang,
Jinxiang Wang,
Yizheng Ye:
An energy-efficient temporal encoding circuit technique for on-chip high performance buses.
ACM Great Lakes Symposium on VLSI 2006: 422-427 |
| 18 | EE | Jianwei Zhang,
Yizheng Ye,
Bin-Da Liu:
A Low-Power Technique Based on Charge Injection and Current-Saving Methods for Match-Line Sensing in Content-Addressable Memories.
APCCAS 2006: 1293-1296 |
| 17 | EE | Qingli Zhang,
Jinxiang Wang,
Yizheng Ye:
Low-Power Crosstalk Avoidance Encoding for On-Chip Data Buses.
APCCAS 2006: 1611-1614 |
| 16 | EE | Tong Zhou,
Zhibo Zhou,
Mingyan Yu,
Yizheng Ye:
Design of A Low Power High Entropy Chaos-Based Truly Random Number Generator.
APCCAS 2006: 1955-1958 |
| 15 | EE | Zhiqiang Gao,
Mingyan Yu,
Yizheng Ye,
Jianguo Ma:
A CMOS bandpass filter with wide-tuning range for wireless applications.
ISCAS 2006 |
| 14 | EE | Shengtian Sang,
Xiaoming Li,
Yizheng Ye:
Dependency driven partitioning objects generation for hardware/software partitioning.
ISCAS 2006 |
| 13 | EE | Guochi Huang,
Tae-Sung Kim,
Byung-Sung Kim,
Mingyan Yu,
Yizheng Ye:
Post linearization of CMOS LNA using double cascade FETs.
ISCAS 2006 |
| 12 | EE | Jianwei Zhang,
Yizheng Ye,
Bin-Da Liu:
A new mismatch-dependent low power technique with shadow match-line voltage-detecting scheme for CAMs.
ISLPED 2006: 135-138 |
| 11 | EE | Tong Zhou,
Mingyan Yu,
Yizheng Ye:
A Pipelined Switched-Current Chaotic System for the High-Speed Truly Random Number Generation in Crypto Processor.
VLSI Design 2006: 216-221 |
| 2005 |
|---|
| 10 | EE | Yong-sheng Wang,
Jinxiang Wang,
Feng-chang Lai,
Yizheng Ye:
Optimal Schemes for ADC BIST Based on Histogram.
Asian Test Symposium 2005: 52-57 |
| 9 | EE | Zhiqiang Gao,
Jianguo Ma,
Yizheng Ye,
Mingyan Yu:
Large tuning band range of high frequency filter for wireless applications.
ISCAS (1) 2005: 384-387 |
| 2003 |
|---|
| 8 | EE | Yong-sheng Wang,
Liyi Xiao,
Mingyan Yu,
Jinxiang Wang,
Yizheng Ye:
A Test Architecture for System-on-a-Chip.
Asian Test Symposium 2003: 506 |
| 2002 |
|---|
| 7 | EE | Xuemei Zhao,
Yizheng Ye:
Design and Realization of a Low Power Register File Using Energy Model.
PATMOS 2002: 268-277 |
| 6 | EE | Liyi Xiao,
Yizheng Ye,
Bin Li:
A New Synchronization Algorithm for VHDL-AMS Simulation.
J. Comput. Sci. Technol. 17(1): 28-37 (2002) |
| 2001 |
|---|
| 5 | EE | Liyi Xiao,
Bin Li,
Yizheng Ye,
Guoyong Huang,
JinJun Guo,
Peng Zhang:
A mixed-signal simulator for VHDL-AMS.
ASP-DAC 2001: 287-292 |
| 4 | EE | Bin Li,
Liyi Xiao,
Yizheng Ye,
Guoyong Huang:
CLUGGS and CLUCR-Two Matrix Solution Methods for General Circuit Simulation.
Annual Simulation Symposium 2001: 78- |
| 2000 |
|---|
| 3 | EE | Liu Songyan,
Zhigang Mao,
Yizheng Ye:
Implementation of Java Card Virtual Machine.
J. Comput. Sci. Technol. 15(6): 591-596 (2000) |
| 1999 |
|---|
| 2 | EE | Zulan Huang,
Yizheng Ye,
Zhigang Mao:
A New Algorithm for Retiming-Based Partial Scan.
Asian Test Symposium 1999: 327- |
| 1998 |
|---|
| 1 | EE | Pingying Zeng,
Zhigang Mao,
Yizheng Ye,
Yuliang Deng:
Test Pattern Generation for Column Compression Multiplier.
Asian Test Symposium 1998: 500-503 |
